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https://github.com/Telecominfraproject/OpenCellular.git
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samus: Support both Proto2A and Proto2B sequencing
Use the board version to implement both power sequence behaviors in order to support both boards with one EC image. The order of bits used to calculate board version was swapped so update the GPIO table to reflect that. BUG=chrome-os-partner:29502 BRANCH=None TEST=build and boot on samus proto2a Change-Id: Ib0f6010163af4b3bf9b39f64c26220aee43618ef Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204869 Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
committed by
chrome-internal-fetch
parent
4702a1d19b
commit
6232d78df5
@@ -97,9 +97,9 @@ const struct gpio_info gpio_list[] = {
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pd_mcu_interrupt},
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/* Other inputs */
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{"BOARD_VERSION1", LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
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{"BOARD_VERSION1", LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
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{"BOARD_VERSION2", LM4_GPIO_Q, (1<<6), GPIO_INPUT, NULL},
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{"BOARD_VERSION3", LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
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{"BOARD_VERSION3", LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
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{"USB1_OC_L", LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
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{"USB1_STATUS_L", LM4_GPIO_E, (1<<6), GPIO_INPUT, NULL},
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{"USB2_OC_L", LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},
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@@ -240,9 +240,9 @@ enum als_id {
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/* Known board versions for system_get_board_version(). */
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enum board_version {
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BOARD_VERSION_PROTO1 = 0,
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BOARD_VERSION_PROTO1B = 1,
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BOARD_VERSION_PROTO1_9 = 2,
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BOARD_VERSION_PROTO_1_9 = 0,
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BOARD_VERSION_PROTO_2_A = 1,
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BOARD_VERSION_PROTO_2_B = 2,
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};
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/* Wireless signals */
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@@ -235,25 +235,47 @@ enum power_state power_handle_state(enum power_state state)
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/* Assert DPWROK */
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gpio_set_level(GPIO_PCH_DPWROK, 1);
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if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
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CPRINTS("timeout waiting for SLP_SUS to deassert");
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chipset_force_g3();
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return POWER_G3;
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/*
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* Proto2B boards added EC control of RSMRST which allows
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* the sequencing to properly wait for SLP_SUS before
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* enabling the 1.05V rail. Prior to this the sequencing
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* had board specific timing requirements that needed the
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* 1.05V rail to be brought up just after DPWROK assertion.
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*/
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if (system_get_board_version() <= BOARD_VERSION_PROTO_2_A) {
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CPRINTS("Proto2A board, using alternate sequencing");
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/* Enable PP1050 rail. */
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gpio_set_level(GPIO_PP1050_EN, 1);
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/* Wait for 1.05V to come up and CPU to notice */
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if (power_wait_signals(IN_PGOOD_PP1050 |
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IN_PCH_SLP_SUS_DEASSERTED)) {
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CPRINTS("timeout waiting for PP1050/SLP_SUS");
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chipset_force_g3();
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}
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} else {
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if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
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CPRINTS("timeout waiting for SLP_SUS deassert");
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chipset_force_g3();
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return POWER_G3;
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}
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/* Enable PP1050 rail. */
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gpio_set_level(GPIO_PP1050_EN, 1);
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/* Wait for 1.05V to come up and CPU to notice */
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if (power_wait_signals(IN_PGOOD_PP1050)) {
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CPRINTS("timeout waiting for PP1050");
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chipset_force_g3();
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return POWER_G3;
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}
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/* Deassert RSMRST# */
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gpio_set_level(GPIO_PCH_RSMRST_L, 1);
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}
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/* Enable PP1050 rail. */
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gpio_set_level(GPIO_PP1050_EN, 1);
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/* Wait for 1.05V to come up and CPU to notice */
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if (power_wait_signals(IN_PGOOD_PP1050)) {
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CPRINTS("timeout waiting for PP1050");
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chipset_force_g3();
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return POWER_G3;
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}
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/* Deassert RSMRST# */
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gpio_set_level(GPIO_PCH_RSMRST_L, 1);
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/* Wait 5ms for SUSCLK to stabilize */
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msleep(5);
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