samus: Support both Proto2A and Proto2B sequencing

Use the board version to implement both power sequence behaviors
in order to support both boards with one EC image.

The order of bits used to calculate board version was swapped so
update the GPIO table to reflect that.

BUG=chrome-os-partner:29502
BRANCH=None
TEST=build and boot on samus proto2a

Change-Id: Ib0f6010163af4b3bf9b39f64c26220aee43618ef
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/204869
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Duncan Laurie
2014-06-17 16:19:20 +08:00
committed by chrome-internal-fetch
parent 4702a1d19b
commit 6232d78df5
3 changed files with 44 additions and 22 deletions

View File

@@ -97,9 +97,9 @@ const struct gpio_info gpio_list[] = {
pd_mcu_interrupt},
/* Other inputs */
{"BOARD_VERSION1", LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
{"BOARD_VERSION1", LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
{"BOARD_VERSION2", LM4_GPIO_Q, (1<<6), GPIO_INPUT, NULL},
{"BOARD_VERSION3", LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
{"BOARD_VERSION3", LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
{"USB1_OC_L", LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
{"USB1_STATUS_L", LM4_GPIO_E, (1<<6), GPIO_INPUT, NULL},
{"USB2_OC_L", LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},

View File

@@ -240,9 +240,9 @@ enum als_id {
/* Known board versions for system_get_board_version(). */
enum board_version {
BOARD_VERSION_PROTO1 = 0,
BOARD_VERSION_PROTO1B = 1,
BOARD_VERSION_PROTO1_9 = 2,
BOARD_VERSION_PROTO_1_9 = 0,
BOARD_VERSION_PROTO_2_A = 1,
BOARD_VERSION_PROTO_2_B = 2,
};
/* Wireless signals */

View File

@@ -235,25 +235,47 @@ enum power_state power_handle_state(enum power_state state)
/* Assert DPWROK */
gpio_set_level(GPIO_PCH_DPWROK, 1);
if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
CPRINTS("timeout waiting for SLP_SUS to deassert");
chipset_force_g3();
return POWER_G3;
/*
* Proto2B boards added EC control of RSMRST which allows
* the sequencing to properly wait for SLP_SUS before
* enabling the 1.05V rail. Prior to this the sequencing
* had board specific timing requirements that needed the
* 1.05V rail to be brought up just after DPWROK assertion.
*/
if (system_get_board_version() <= BOARD_VERSION_PROTO_2_A) {
CPRINTS("Proto2A board, using alternate sequencing");
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050 |
IN_PCH_SLP_SUS_DEASSERTED)) {
CPRINTS("timeout waiting for PP1050/SLP_SUS");
chipset_force_g3();
}
} else {
if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
CPRINTS("timeout waiting for SLP_SUS deassert");
chipset_force_g3();
return POWER_G3;
}
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050)) {
CPRINTS("timeout waiting for PP1050");
chipset_force_g3();
return POWER_G3;
}
/* Deassert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 1);
}
/* Enable PP1050 rail. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for 1.05V to come up and CPU to notice */
if (power_wait_signals(IN_PGOOD_PP1050)) {
CPRINTS("timeout waiting for PP1050");
chipset_force_g3();
return POWER_G3;
}
/* Deassert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 1);
/* Wait 5ms for SUSCLK to stabilize */
msleep(5);