mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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stm32: add flash driver for stm32f100 SoC
Implementation of the flash driver for the stm32f100 chip used on Snow board. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8865 TEST=On Snow board, use "flashwrite/flasherase" commands from EC console and verify result with "rw" command. Change-Id: Ie8b8be3d549ff9ec8c3036d5f4a97480daa5e03e
This commit is contained in:
Vincent Palatin
@@ -14,6 +14,9 @@
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/* Use USART1 as console serial port */
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#define CONFIG_CONSOLE_UART 1
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/* support programming on-chip flash */
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#define CONFIG_FLASH
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/* use I2C for host communication */
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#define CONFIG_I2C
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259
chip/stm32/flash-stm32f100.c
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259
chip/stm32/flash-stm32f100.c
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@@ -0,0 +1,259 @@
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/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Flash memory module for Chrome EC */
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#include "console.h"
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#include "flash.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#include "watchdog.h"
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#define FLASH_WRITE_BYTES 2
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#define FLASH_ERASE_BYTES 1024
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#define FLASH_PROTECT_BYTES 4096
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#define US_PER_SECOND 1000000
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/* the approximate number of CPU cycles per iteration of the loop when polling
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* the flash status
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*/
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#define CYCLE_PER_FLASH_LOOP 10
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/* Flash page programming timeout. This is 2x the datasheet max. */
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#define FLASH_TIMEOUT_US 16000
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#define FLASH_TIMEOUT_LOOP \
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(FLASH_TIMEOUT_US * (CPU_CLOCK / US_PER_SECOND) / CYCLE_PER_FLASH_LOOP)
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/* Flash unlocking keys */
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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/* Lock bits*/
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#define CR_LOCK (1<<7)
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#define PRG_LOCK 0
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#define OPT_LOCK (1<<9)
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int flash_get_write_block_size(void)
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{
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return FLASH_WRITE_BYTES;
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}
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int flash_get_erase_block_size(void)
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{
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return FLASH_ERASE_BYTES;
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}
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int flash_get_protect_block_size(void)
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{
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BUILD_ASSERT(FLASH_PROTECT_BYTES == CONFIG_FLASH_BANK_SIZE);
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return FLASH_PROTECT_BYTES;
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}
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int flash_physical_size(void)
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{
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return CONFIG_FLASH_SIZE;
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}
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int flash_physical_read(int offset, int size, char *data)
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{
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/* Just read the flash from its memory window. */
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/* TODO: (crosbug.com/p/7473) is this affected by data cache? */
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memcpy(data, (char *)offset, size);
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return EC_SUCCESS;
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}
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static int unlock(int locks)
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{
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/* unlock CR if needed */
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if (STM32_FLASH_CR & CR_LOCK) {
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STM32_FLASH_KEYR = KEY1;
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STM32_FLASH_KEYR = KEY2;
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}
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/* unlock option memory if required */
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if ((locks & OPT_LOCK) && !(STM32_FLASH_CR & OPT_LOCK)) {
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STM32_FLASH_OPTKEYR = KEY1;
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STM32_FLASH_OPTKEYR = KEY2;
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}
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return ((STM32_FLASH_CR ^ OPT_LOCK) & (locks | CR_LOCK)) ?
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EC_ERROR_UNKNOWN : EC_SUCCESS;
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}
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static void lock(void)
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{
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STM32_FLASH_CR = CR_LOCK;
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}
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static uint8_t read_optb(int byte)
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{
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return *(uint8_t *)(STM32_OPTB_BASE + byte);
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}
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static void write_optb(int byte, uint8_t value)
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{
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volatile int16_t *hword = (uint16_t *)(STM32_OPTB_BASE + byte);
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if (unlock(OPT_LOCK) != EC_SUCCESS)
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return;
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/* set OPTPG bit */
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STM32_FLASH_CR |= (1<<4);
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/*TODO: how do we manage erasing (aka OPTER) ? */
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*hword = value ;
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/* reset OPTPG bit */
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STM32_FLASH_CR |= (1<<4);
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lock();
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}
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int flash_physical_write(int offset, int size, const char *data)
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{
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/* this is pretty nasty, we need to enforce alignment instead of this
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* wild cast : TODO crosbug.com/p/9526
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*/
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uint16_t *data16 = (uint16_t *)data;
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uint16_t *address = (uint16_t *)(CONFIG_FLASH_BASE + offset);
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int res = EC_SUCCESS;
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int i;
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if (unlock(PRG_LOCK) != EC_SUCCESS) {
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res = EC_ERROR_UNKNOWN;
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goto exit_wr;
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}
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/* Clear previous error status */
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STM32_FLASH_SR = 0x34;
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/* set PG bit */
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STM32_FLASH_CR |= (1<<0);
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for ( ; size > 0; size -= FLASH_WRITE_BYTES) {
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#ifdef CONFIG_TASK_WATCHDOG
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/* Reload the watchdog timer to avoid watchdog reset when doing
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* long writing with interrupt disabled.
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*/
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watchdog_reload();
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#endif
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/* wait to be ready */
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for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP) ;
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i++)
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;
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/* write the half word */
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*address++ = *data16++;
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/* Wait for writes to complete */
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for (i = 0; (STM32_FLASH_SR & 1) && (i < FLASH_TIMEOUT_LOOP) ;
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i++)
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;
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if (STM32_FLASH_SR & 1) {
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res = EC_ERROR_TIMEOUT;
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goto exit_wr;
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}
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/* Check for error conditions - erase failed, voltage error,
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* protection error */
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if (STM32_FLASH_SR & 0x14) {
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res = EC_ERROR_UNKNOWN;
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goto exit_wr;
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}
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}
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exit_wr:
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/* Disable PG bit */
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STM32_FLASH_CR &= ~(1<<0);
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lock();
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return res;
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}
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int flash_physical_erase(int offset, int size)
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{
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uint32_t address;
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int res = EC_SUCCESS;
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if (unlock(PRG_LOCK) != EC_SUCCESS)
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return EC_ERROR_UNKNOWN;
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/* Clear previous error status */
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STM32_FLASH_SR = 0x34;
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/* set PER bit */
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STM32_FLASH_CR |= (1<<1);
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for (address = CONFIG_FLASH_BASE + offset ;
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size > 0; size -= FLASH_ERASE_BYTES,
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address += FLASH_ERASE_BYTES) {
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timestamp_t deadline;
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/* select page to erase */
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STM32_FLASH_AR = address;
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/* set STRT bit : start erase */
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STM32_FLASH_CR |= (1<<6);
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#ifdef CONFIG_TASK_WATCHDOG
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/* Reload the watchdog timer in case the erase takes long time
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* so that erasing many flash pages
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*/
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watchdog_reload();
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#endif
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deadline.val = get_time().val + FLASH_TIMEOUT_US;
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/* Wait for erase to complete */
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while ((STM32_FLASH_SR & 1) &&
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(get_time().val < deadline.val)) {
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usleep(300);
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}
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if (STM32_FLASH_SR & 1) {
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res = EC_ERROR_TIMEOUT;
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goto exit_er;
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}
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/* Check for error conditions - erase failed, voltage error,
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* protection error */
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if (STM32_FLASH_SR & 0x14) {
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res = EC_ERROR_UNKNOWN;
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goto exit_er;
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}
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}
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exit_er:
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/* reset PER bit */
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STM32_FLASH_CR &= ~(1<<1);
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lock();
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return res;
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}
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int flash_physical_get_protect(int block)
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{
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uint8_t val = read_optb(STM32_OPTB_WRP_OFF(block/8));
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return val & (1 << (block % 8));
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}
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void flash_physical_set_protect(int block)
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{
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int byte_off = STM32_OPTB_WRP_OFF(block/8);
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uint8_t val = read_optb(byte_off) | (1 << (block % 8));
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write_optb(byte_off, val);
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}
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