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Ryu: i2c speed to 1MHz

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To avoid FIFO errors - the fifo becomes full will we wait for the AP
to read the vectors, increase the i2c speed between EC and AP.
Target 1Mhz, 400KHz observed due to a limitation of the Tegra I2C
controller.

BRANCH=smaug
TEST=Verify with analyzer that speed is now 400KHz.
The duty cycle is still not right.
Check that FIFO underrun do not happen during tests.
BUG=chrome-os-partner:40280,chrome-os-partner:39233,chrome-os-partner:39900

Change-Id: Id6c2dfb10c34a919ec99a58bc0082207f7748b7e
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/284613
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Gwendal Grignou
2015-06-25 14:15:08 -07:00
committed by ChromeOS Commit Bot
parent ad099a3cf2
commit 7015336ea8
2 changed files with 2 additions and 2 deletions
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2
board/ryu/board.c
View File

@@ -268,7 +268,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100,
GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
{"slave", I2C_PORT_SLAVE, 100,
{"slave", I2C_PORT_SLAVE, 1000,
GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);

2
chip/stm32/i2c-stm32f0.c
View File

@@ -78,7 +78,7 @@ static void i2c_set_freq_port(const struct i2c_port_t *p)
/* Set clock frequency */
switch (p->kbps) {
case 1000:
STM32_I2C_TIMINGR(port) = 0x50110103;
STM32_I2C_TIMINGR(port) = 0x50100103;
break;
case 400:
STM32_I2C_TIMINGR(port) = 0x50330309;