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bolt: force SYS_PWROK and PP3300_DSW_GATED_EN to 0 in forcing G3 path

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The following signals were not being initialized properly in the
forcing G3 path:
- GPIO_SYS_PWROK
- GPIO_PP3300_DSW_GATED_EN
This lead to the EC RW sysjump, but the boards wouldn't reboot
on the x86 side. Sadly, without this change, the board I have
works. However, those signals need to be driven low.

BUG=chrome-os-partner:20372
BRANCH=None
TEST=Willis tested on boards that previously didn't work.

Change-Id: I1771881485bc5be73ed2b08da91fddff9ab09167
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63845
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Aaron Durbin
2013-07-30 21:06:48 -05:00
committed by ChromeBot
parent 86bef29c3d
commit 706f121146
1 changed files with 2 additions and 0 deletions
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2
board/bolt/power_sequence.c
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@@ -127,11 +127,13 @@ enum x86_state x86_chipset_init(void)
/* Force all signals to their G3 states */
CPRINTF("[%T x86 forcing G3]\n");
gpio_set_level(GPIO_PCH_PWROK, 0);
gpio_set_level(GPIO_SYS_PWROK, 0);
gpio_set_level(GPIO_VCORE_EN, 0);
gpio_set_level(GPIO_PP1050_EN, 0);
gpio_set_level(GPIO_PP1350_EN, 0);
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
gpio_set_level(GPIO_PCH_DPWROK, 0);
wireless_enable(0);