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Merge "introducing chip variant for stm32 family [1/3]"

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This commit is contained in:
Gerrit
2012-05-01 17:08:27 -07:00
committed by Gerrit Code Review
parent 306e9632f9 539c397fb1
commit 709eee03f5
22 changed files with 538 additions and 538 deletions
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4
board/adv/board.c
View File

@@ -69,8 +69,8 @@ void configure_board(void)
/* Enable all GPIOs clocks
* TODO: more fine-grained enabling for power saving
*/
STM32L_RCC_AHBENR |= 0x3f;
STM32L_RCC_APB2ENR |= 0x01;
STM32_RCC_AHBENR |= 0x3f;
STM32_RCC_APB2ENR |= 0x01;
/* Select Alternate function for USART2 on pins PA2/PA3 */
gpio_set_alternate_function(GPIO_A, (1<<2) | (1<<3), GPIO_ALT_USART);

2
board/adv/build.mk
View File

@@ -5,6 +5,6 @@
# Board specific files build
# the IC is STmicro STM32L151R8H6
CHIP:=stm32l
CHIP:=stm32
board-y=board.o

30
board/daisy/board.c
View File

@@ -89,20 +89,20 @@ void configure_board(void)
/* Enable all GPIOs clocks
* TODO: more fine-grained enabling for power saving
*/
STM32L_RCC_AHBENR |= 0x3f;
STM32_RCC_AHBENR |= 0x3f;
/* Required to configure external IRQ lines (SYSCFG_EXTICRn) */
/* FIXME: This seems to break USB download in U-Boot (?!?) */
STM32L_RCC_APB2ENR |= 1 << 0;
STM32_RCC_APB2ENR |= 1 << 0;
/* Enable SPI */
STM32L_RCC_APB2ENR |= (1<<12);
STM32_RCC_APB2ENR |= (1<<12);
/* SPI1 on pins PA4-7 (push-pull, no pullup/down, 10MHz) */
STM32L_GPIO_PUPDR_OFF(GPIO_A) &= ~((2 << (7 * 2)) |
STM32_GPIO_PUPDR_OFF(GPIO_A) &= ~((2 << (7 * 2)) |
(2 << (6 * 2)) |
(2 << (5 * 2)) |
(2 << (4 * 2)));
STM32L_GPIO_OTYPER_OFF(GPIO_A) &= ~((1 << 7) |
STM32_GPIO_OTYPER_OFF(GPIO_A) &= ~((1 << 7) |
(1 << 6) |
(1 << 5) |
(1 << 4));
@@ -110,27 +110,27 @@ void configure_board(void)
(1<<6) |
(1<<5) |
(1<<4), GPIO_ALT_SPI);
STM32L_GPIO_OSPEEDR_OFF(GPIO_A) |= 0xff00;
STM32_GPIO_OSPEEDR_OFF(GPIO_A) |= 0xff00;
/*
* I2C SCL/SDA on PB10-11, bi-directional, no pull-up/down, initialized
* as hi-Z until alt. function is set
*/
STM32L_GPIO_PUPDR_OFF(GPIO_B) &= ~((3 << (11*2)) | (3 << (10*2)));
STM32L_GPIO_MODER_OFF(GPIO_B) &= ~((3 << (11*2)) | (3 << (10*2)));
STM32L_GPIO_MODER_OFF(GPIO_B) |= (1 << (11*2)) | (1 << (10*2));
STM32L_GPIO_OTYPER_OFF(GPIO_B) |= (1<<11) | (1<<10);
STM32L_GPIO_BSRR_OFF(GPIO_B) |= (1<<11) | (1<<10);
STM32_GPIO_PUPDR_OFF(GPIO_B) &= ~((3 << (11*2)) | (3 << (10*2)));
STM32_GPIO_MODER_OFF(GPIO_B) &= ~((3 << (11*2)) | (3 << (10*2)));
STM32_GPIO_MODER_OFF(GPIO_B) |= (1 << (11*2)) | (1 << (10*2));
STM32_GPIO_OTYPER_OFF(GPIO_B) |= (1<<11) | (1<<10);
STM32_GPIO_BSRR_OFF(GPIO_B) |= (1<<11) | (1<<10);
gpio_set_alternate_function(GPIO_B, (1<<11) | (1<<10), GPIO_ALT_I2C);
/* Select Alternate function for USART1 on pins PA9/PA10 */
gpio_set_alternate_function(GPIO_A, (1<<9) | (1<<10), GPIO_ALT_USART);
/* EC_INT is output, open-drain */
STM32L_GPIO_OTYPER_OFF(GPIO_B) |= (1<<9);
STM32L_GPIO_PUPDR_OFF(GPIO_B) &= ~(0x3 << (2*9));
STM32L_GPIO_MODER_OFF(GPIO_B) &= ~(0x3 << (2*9));
STM32L_GPIO_MODER_OFF(GPIO_B) |= 0x1 << (2*9);
STM32_GPIO_OTYPER_OFF(GPIO_B) |= (1<<9);
STM32_GPIO_PUPDR_OFF(GPIO_B) &= ~(0x3 << (2*9));
STM32_GPIO_MODER_OFF(GPIO_B) &= ~(0x3 << (2*9));
STM32_GPIO_MODER_OFF(GPIO_B) |= 0x1 << (2*9);
/* put GPIO in Hi-Z state */
gpio_set_level(GPIO_EC_INT, 1);
}

2
board/daisy/build.mk
View File

@@ -5,6 +5,6 @@
# Board specific files build
# the IC is STmicro STM32L151R8H6
CHIP:=stm32l
CHIP:=stm32
board-y=board.o

6
board/discovery/board.c
View File

@@ -53,9 +53,9 @@ void configure_board(void)
* GPIO clocks in low-power (sleep) mode.
* TODO: more fine-grained enabling for power saving
*/
STM32L_RCC_AHBENR |= 0x3f;
STM32L_RCC_AHBLPENR |= 0x0e;
STM32L_RCC_APB2ENR |= 0x01;
STM32_RCC_AHBENR |= 0x3f;
STM32_RCC_AHBLPENR |= 0x0e;
STM32_RCC_APB2ENR |= 0x01;
#if CONFIG_CONSOLE_UART == 1
/* Select Alternate function for USART1 on pins PA9/PA10 */

2
board/discovery/build.mk
View File

@@ -5,6 +5,6 @@
# Board specific files build
# the IC is STmicro STM32L151R8H6
CHIP:=stm32l
CHIP:=stm32
board-y=board.o

4
chip/stm32l/build.mk → chip/stm32/build.mk
View File

@@ -2,10 +2,10 @@
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# STM32L chip specific files build
# STM32 chip specific files build
#
# STM32L15xx SoC family has a Cortex-M3 ARM core
# STM32 SoC family has a Cortex-M3 ARM core
CORE:=cortex-m
chip-y=clock.o dma.o gpio.o hwtimer.o jtag.o system.o uart.o

24
chip/stm32l/clock.c → chip/stm32/clock.c
View File

@@ -24,11 +24,11 @@ int clock_init(void)
*/
/* Ensure that HSI is ON */
if (!(STM32L_RCC_CR & (1 << 1))) {
if (!(STM32_RCC_CR & (1 << 1))) {
/* Enable HSI */
STM32L_RCC_CR |= 1 << 0;
STM32_RCC_CR |= 1 << 0;
/* Wait for HSI to be ready */
while (!(STM32L_RCC_CR & (1 << 1)))
while (!(STM32_RCC_CR & (1 << 1)))
;
}
@@ -38,32 +38,32 @@ int clock_init(void)
* but it is faster not to read-back the value of the ACR register
* in the middle of the sequence so let's use a temporary variable.
*/
tmp_acr = STM32L_FLASH_ACR;
tmp_acr = STM32_FLASH_ACR;
/* Enable 64-bit access */
tmp_acr |= (1 << 2);
STM32L_FLASH_ACR = tmp_acr;
STM32_FLASH_ACR = tmp_acr;
/* Enable Prefetch Buffer */
tmp_acr |= (1 << 1);
STM32L_FLASH_ACR = tmp_acr;
STM32_FLASH_ACR = tmp_acr;
/* Flash 1 wait state */
tmp_acr |= (1 << 0);
STM32L_FLASH_ACR = tmp_acr;
STM32_FLASH_ACR = tmp_acr;
/*
* stays on HSI, no prescaler, PLLSRC = HSI, PLLMUL = x3, PLLDIV = /3,
* no MCO => PLLVCO = 48 MHz and PLLCLK = 16 Mhz
*/
BUILD_ASSERT(CPU_CLOCK == 16000000);
STM32L_RCC_CFGR = 0x00800001;
STM32_RCC_CFGR = 0x00800001;
/* Enable the PLL */
STM32L_RCC_CR |= 1 << 24;
STM32_RCC_CR |= 1 << 24;
/* Wait for the PLL to lock */
while (!(STM32L_RCC_CR & (1 << 25)))
while (!(STM32_RCC_CR & (1 << 25)))
;
/* switch to SYSCLK to the PLL */
STM32L_RCC_CFGR = 0x00800003;
STM32_RCC_CFGR = 0x00800003;
/* wait until the PLL is the clock source */
while ((STM32L_RCC_CFGR & 0xc) != 0xc)
while ((STM32_RCC_CFGR & 0xc) != 0xc)
;
return EC_SUCCESS;

0
chip/stm32l/config.h → chip/stm32/config.h
View File

6
chip/stm32l/dma.c → chip/stm32/dma.c
View File

@@ -27,10 +27,10 @@ static struct dma_channel *get_channel(int channel)
/* Get a pointer to the correct controller and channel */
ASSERT(channel < DMA_NUM_CHANNELS);
if (channel < DMA1_NUM_CHANNELS) {
dma = (struct dma_ctlr *)STM32L_DMA1_BASE;
dma = (struct dma_ctlr *)STM32_DMA1_BASE;
chan = &dma->chan[channel];
} else {
dma = (struct dma_ctlr *)STM32L_DMA2_BASE;
dma = (struct dma_ctlr *)STM32_DMA2_BASE;
chan = &dma->chan[channel - DMA1_NUM_CHANNELS];
}
@@ -166,5 +166,5 @@ void dma_test(void)
void dma_init(void)
{
/* Enable DMA1, we don't support DMA2 yet */
STM32L_RCC_AHBENR |= 1 << 24;
STM32_RCC_AHBENR |= 1 << 24;
}

12
chip/stm32l/dma.h → chip/stm32/dma.h
View File

@@ -2,11 +2,11 @@
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Register map and API for STM32L processor dma registers
* Register map and API for STM32 processor dma registers
*/
#ifndef __STM32L_DMA
#define __STM32L_DMA
#ifndef __STM32_DMA
#define __STM32_DMA
#include "common.h"
@@ -67,13 +67,13 @@ enum {
*/
/**
* @param spi SPI port to request: STM32L_SPI1_PORT or STM32L_SPI2_PORT
* @param spi SPI port to request: STM32_SPI1_PORT or STM32_SPI2_PORT
* @return DMA channel to use for rx / tx on that port
*/
#define DMA_CHANNEL_FOR_SPI_RX(spi) \
((spi) == STM32L_SPI1_PORT ? DMAC_SPI1_RX : DMAC_SPI2_RX)
((spi) == STM32_SPI1_PORT ? DMAC_SPI1_RX : DMAC_SPI2_RX)
#define DMA_CHANNEL_FOR_SPI_TX(spi) \
((spi) == STM32L_SPI1_PORT ? DMAC_SPI1_TX : DMAC_SPI2_TX)
((spi) == STM32_SPI1_PORT ? DMAC_SPI1_TX : DMAC_SPI2_TX)
/**
* Start a DMA transfer to transmit data from memory to a peripheral

72
chip/stm32l/gpio.c → chip/stm32/gpio.c
View File

@@ -31,43 +31,43 @@ int gpio_pre_init(void)
/* Enable all GPIOs clocks
* TODO: more fine-grained enabling for power saving
*/
STM32L_RCC_AHBENR |= 0x3f;
STM32_RCC_AHBENR |= 0x3f;
for (i = 0; i < GPIO_COUNT; i++, g++) {
/* bitmask for registers with 2 bits per GPIO pin */
uint32_t mask2 = (g->mask * g->mask) | (g->mask * g->mask * 2);
uint32_t val;
val = STM32L_GPIO_PUPDR_OFF(g->port) & ~mask2;
val = STM32_GPIO_PUPDR_OFF(g->port) & ~mask2;
if (g->flags & GPIO_PULL_UP) /* Pull Up = 01 */
val |= 0x55555555 & mask2;
else if (g->flags & GPIO_PULL_DOWN) /* Pull Down = 10 */
val |= 0xaaaaaaaa & mask2;
STM32L_GPIO_PUPDR_OFF(g->port) = val;
STM32_GPIO_PUPDR_OFF(g->port) = val;
if (g->flags & GPIO_OPEN_DRAIN)
STM32L_GPIO_OTYPER_OFF(g->port) |= g->mask;
STM32_GPIO_OTYPER_OFF(g->port) |= g->mask;
/*
* Set pin level after port has been set up as to avoid
* potential damage, e.g. driving an open-drain output
* high before it has been configured as such.
*/
val = STM32L_GPIO_MODER_OFF(g->port) & ~mask2;
val = STM32_GPIO_MODER_OFF(g->port) & ~mask2;
if (g->flags & GPIO_OUTPUT) { /* General purpose, MODE = 01 */
val |= 0x55555555 & mask2;
STM32L_GPIO_MODER_OFF(g->port) = val;
STM32_GPIO_MODER_OFF(g->port) = val;
gpio_set_level(i, g->flags & GPIO_HIGH);
} else if (g->flags & GPIO_INPUT) { /* Input, MODE=00 */
STM32L_GPIO_MODER_OFF(g->port) = val;
STM32_GPIO_MODER_OFF(g->port) = val;
}
/* Set up interrupts if necessary */
ASSERT(!(g->flags & GPIO_INT_LEVEL));
if (g->flags & (GPIO_INT_RISING | GPIO_INT_BOTH))
STM32L_EXTI_RTSR |= g->mask;
STM32_EXTI_RTSR |= g->mask;
if (g->flags & (GPIO_INT_FALLING | GPIO_INT_BOTH))
STM32L_EXTI_FTSR |= g->mask;
STM32_EXTI_FTSR |= g->mask;
/* Interrupt is enabled by gpio_enable_interrupt() */
}
@@ -78,13 +78,13 @@ int gpio_pre_init(void)
static int gpio_init(void)
{
/* Enable IRQs now that pins are set up */
task_enable_irq(STM32L_IRQ_EXTI0);
task_enable_irq(STM32L_IRQ_EXTI1);
task_enable_irq(STM32L_IRQ_EXTI2);
task_enable_irq(STM32L_IRQ_EXTI3);
task_enable_irq(STM32L_IRQ_EXTI4);
task_enable_irq(STM32L_IRQ_EXTI9_5);
task_enable_irq(STM32L_IRQ_EXTI15_10);
task_enable_irq(STM32_IRQ_EXTI0);
task_enable_irq(STM32_IRQ_EXTI1);
task_enable_irq(STM32_IRQ_EXTI2);
task_enable_irq(STM32_IRQ_EXTI3);
task_enable_irq(STM32_IRQ_EXTI4);
task_enable_irq(STM32_IRQ_EXTI9_5);
task_enable_irq(STM32_IRQ_EXTI15_10);
return EC_SUCCESS;
}
@@ -96,11 +96,11 @@ void gpio_set_alternate_function(int port, int mask, int func)
int bit;
uint8_t half;
uint32_t afr;
uint32_t moder = STM32L_GPIO_MODER_OFF(port);
uint32_t moder = STM32_GPIO_MODER_OFF(port);
/* Low half of the GPIO bank */
half = mask & 0xff;
afr = STM32L_GPIO_AFRL_OFF(port);
afr = STM32_GPIO_AFRL_OFF(port);
while (half) {
bit = 31 - __builtin_clz(half);
afr &= ~(0xf << (bit * 4));
@@ -109,11 +109,11 @@ void gpio_set_alternate_function(int port, int mask, int func)
moder |= 0x2 << (bit * 2 + 0);
half &= ~(1 << bit);
}
STM32L_GPIO_AFRL_OFF(port) = afr;
STM32_GPIO_AFRL_OFF(port) = afr;
/* High half of the GPIO bank */
half = mask >> 8;
afr = STM32L_GPIO_AFRH_OFF(port);
afr = STM32_GPIO_AFRH_OFF(port);
while (half) {
bit = 31 - __builtin_clz(half);
afr &= ~(0xf << (bit * 4));
@@ -122,21 +122,21 @@ void gpio_set_alternate_function(int port, int mask, int func)
moder |= 0x2 << (bit * 2 + 16);
half &= ~(1 << bit);
}
STM32L_GPIO_AFRH_OFF(port) = afr;
STM32L_GPIO_MODER_OFF(port) = moder;
STM32_GPIO_AFRH_OFF(port) = afr;
STM32_GPIO_MODER_OFF(port) = moder;
}
int gpio_get_level(enum gpio_signal signal)
{
return !!(STM32L_GPIO_IDR_OFF(gpio_list[signal].port) &
return !!(STM32_GPIO_IDR_OFF(gpio_list[signal].port) &
gpio_list[signal].mask);
}
int gpio_set_level(enum gpio_signal signal, int value)
{
STM32L_GPIO_BSRR_OFF(gpio_list[signal].port) =
STM32_GPIO_BSRR_OFF(gpio_list[signal].port) =
gpio_list[signal].mask << (value ? 0 : 16);
return EC_SUCCESS;
@@ -163,10 +163,10 @@ int gpio_enable_interrupt(enum gpio_signal signal)
group = bit / 4;
shift = (bit % 4) * 4;
bank = (g->port - STM32L_GPIOA_BASE) / 0x400;
STM32L_SYSCFG_EXTICR(group) = (STM32L_SYSCFG_EXTICR(group) &
bank = (g->port - STM32_GPIOA_BASE) / 0x400;
STM32_SYSCFG_EXTICR(group) = (STM32_SYSCFG_EXTICR(group) &
~(0xF << shift)) | (bank << shift);
STM32L_EXTI_IMR |= g->mask;
STM32_EXTI_IMR |= g->mask;
return EC_SUCCESS;
}
@@ -178,9 +178,9 @@ static void gpio_interrupt(void)
{
int bit;
const struct gpio_info *g;
uint32_t pending = STM32L_EXTI_PR;
uint32_t pending = STM32_EXTI_PR;
STM32L_EXTI_PR = pending;
STM32_EXTI_PR = pending;
while (pending) {
bit = 31 - __builtin_clz(pending);
@@ -190,10 +190,10 @@ static void gpio_interrupt(void)
pending &= ~(1 << bit);
}
}
DECLARE_IRQ(STM32L_IRQ_EXTI0, gpio_interrupt, 1);
DECLARE_IRQ(STM32L_IRQ_EXTI1, gpio_interrupt, 1);
DECLARE_IRQ(STM32L_IRQ_EXTI2, gpio_interrupt, 1);
DECLARE_IRQ(STM32L_IRQ_EXTI3, gpio_interrupt, 1);
DECLARE_IRQ(STM32L_IRQ_EXTI4, gpio_interrupt, 1);
DECLARE_IRQ(STM32L_IRQ_EXTI9_5, gpio_interrupt, 1);
DECLARE_IRQ(STM32L_IRQ_EXTI15_10, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI0, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI1, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI2, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI3, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI4, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI9_5, gpio_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI15_10, gpio_interrupt, 1);

84
chip/stm32l/hwtimer.c → chip/stm32/hwtimer.c
View File

@@ -24,26 +24,26 @@ void __hw_clock_event_set(uint32_t deadline)
{
last_deadline = deadline;
if ((deadline >> 16) == STM32L_TIM_CNT(2)) {
if ((deadline >> 16) == STM32_TIM_CNT(2)) {
/* we can set a match on the LSB only */
STM32L_TIM_CCR1(3) = deadline & 0xffff;
STM32_TIM_CCR1(3) = deadline & 0xffff;
/* disable MSB match */
STM32L_TIM_DIER(2) &= ~2;
STM32_TIM_DIER(2) &= ~2;
/* Clear the match flags */
STM32L_TIM_SR(2) = ~2;
STM32L_TIM_SR(3) = ~2;
STM32_TIM_SR(2) = ~2;
STM32_TIM_SR(3) = ~2;
/* Set the match interrupt */
STM32L_TIM_DIER(3) |= 2;
} else if ((deadline >> 16) > STM32L_TIM_CNT(2)) {
STM32_TIM_DIER(3) |= 2;
} else if ((deadline >> 16) > STM32_TIM_CNT(2)) {
/* first set a match on the MSB */
STM32L_TIM_CCR1(2) = deadline >> 16;
STM32_TIM_CCR1(2) = deadline >> 16;
/* disable LSB match */
STM32L_TIM_DIER(3) &= ~2;
STM32_TIM_DIER(3) &= ~2;
/* Clear the match flags */
STM32L_TIM_SR(2) = ~2;
STM32L_TIM_SR(3) = ~2;
STM32_TIM_SR(2) = ~2;
STM32_TIM_SR(3) = ~2;
/* Set the match interrupt */
STM32L_TIM_DIER(2) |= 2;
STM32_TIM_DIER(2) |= 2;
}
}
@@ -55,8 +55,8 @@ uint32_t __hw_clock_event_get(void)
void __hw_clock_event_clear(void)
{
/* Disable the match interrupts */
STM32L_TIM_DIER(3) &= ~2;
STM32L_TIM_DIER(2) &= ~2;
STM32_TIM_DIER(3) &= ~2;
STM32_TIM_DIER(2) &= ~2;
}
uint32_t __hw_clock_source_read(void)
@@ -66,20 +66,20 @@ uint32_t __hw_clock_source_read(void)
/* ensure the two half-words are coherent */
do {
hi = STM32L_TIM_CNT(2);
lo = STM32L_TIM_CNT(3);
} while (hi != STM32L_TIM_CNT(2));
hi = STM32_TIM_CNT(2);
lo = STM32_TIM_CNT(3);
} while (hi != STM32_TIM_CNT(2));
return (hi << 16) | lo;
}
static void __hw_clock_source_irq(void)
{
uint32_t stat_tim2 = STM32L_TIM_SR(2);
uint32_t stat_tim2 = STM32_TIM_SR(2);
/* clear status */
STM32L_TIM_SR(3) = 0;
STM32L_TIM_SR(2) = 0;
STM32_TIM_SR(3) = 0;
STM32_TIM_SR(2) = 0;
/*
* Find expired timers and set the new timer deadline
@@ -87,8 +87,8 @@ static void __hw_clock_source_irq(void)
*/
process_timers(stat_tim2 & 0x01);
}
DECLARE_IRQ(STM32L_IRQ_TIM2, __hw_clock_source_irq, 1);
DECLARE_IRQ(STM32L_IRQ_TIM3, __hw_clock_source_irq, 1);
DECLARE_IRQ(STM32_IRQ_TIM2, __hw_clock_source_irq, 1);
DECLARE_IRQ(STM32_IRQ_TIM3, __hw_clock_source_irq, 1);
int __hw_clock_source_init(void)
{
@@ -99,44 +99,44 @@ int __hw_clock_source_init(void)
*/
/* Enable TIM2 and TIM3 clocks */
STM32L_RCC_APB1ENR |= 0x3;
STM32_RCC_APB1ENR |= 0x3;
/*
* Timer configuration : Upcounter, counter disabled, update event only
* on overflow.
*/
STM32L_TIM_CR1(2) = 0x0004;
STM32L_TIM_CR1(3) = 0x0004;
STM32_TIM_CR1(2) = 0x0004;
STM32_TIM_CR1(3) = 0x0004;
/* TIM3 (master mode) generates a periodic trigger signal on each UEV */
STM32L_TIM_CR2(2) = 0x0000;
STM32L_TIM_CR2(3) = 0x0020;
STM32_TIM_CR2(2) = 0x0000;
STM32_TIM_CR2(3) = 0x0020;
/* TIM2 (slave mode) uses ITR2 as internal trigger */
STM32L_TIM_SMCR(2) = 0x0027;
STM32L_TIM_SMCR(3) = 0x0000;
STM32_TIM_SMCR(2) = 0x0027;
STM32_TIM_SMCR(3) = 0x0000;
/* Auto-reload value : 16-bit free-running counters */
STM32L_TIM_ARR(2) = 0xffff;
STM32L_TIM_ARR(3) = 0xffff;
STM32_TIM_ARR(2) = 0xffff;
STM32_TIM_ARR(3) = 0xffff;
/* Pre-scaler value :
* TIM3 is counting microseconds, TIM2 is counting every TIM3 overflow.
*/
STM32L_TIM_PSC(2) = 0;
STM32L_TIM_PSC(3) = CLOCKSOURCE_DIVIDER - 1;
STM32_TIM_PSC(2) = 0;
STM32_TIM_PSC(3) = CLOCKSOURCE_DIVIDER - 1;
/* Reload the pre-scaler */
STM32L_TIM_EGR(2) = 0x0000;
STM32L_TIM_EGR(3) = 0x0000;
STM32_TIM_EGR(2) = 0x0000;
STM32_TIM_EGR(3) = 0x0000;
/* setup the overflow interrupt on TIM2 */
STM32L_TIM_DIER(2) = 0x0001;
STM32L_TIM_DIER(3) = 0x0000;
STM32_TIM_DIER(2) = 0x0001;
STM32_TIM_DIER(3) = 0x0000;
/* Start counting */
STM32L_TIM_CR1(2) |= 1;
STM32L_TIM_CR1(3) |= 1;
STM32_TIM_CR1(2) |= 1;
STM32_TIM_CR1(3) |= 1;
/* Enable timer interrupts */
task_enable_irq(STM32L_IRQ_TIM2);
task_enable_irq(STM32L_IRQ_TIM3);
task_enable_irq(STM32_IRQ_TIM2);
task_enable_irq(STM32_IRQ_TIM3);
return STM32L_IRQ_TIM3;
return STM32_IRQ_TIM3;
}

50
chip/stm32l/i2c.c → chip/stm32/i2c.c
View File

@@ -27,8 +27,8 @@
#define I2C_CCR (CPU_CLOCK/(2 * I2C_FREQ))
#define NUM_PORTS 2
#define I2C1 STM32L_I2C1_PORT
#define I2C2 STM32L_I2C2_PORT
#define I2C1 STM32_I2C1_PORT
#define I2C2 STM32_I2C2_PORT
static task_id_t task_waiting_on_port[NUM_PORTS];
static struct mutex port_mutex[NUM_PORTS];
@@ -53,14 +53,14 @@ static uint8_t out_msg[32];
static void wait_rx(int port)
{
/* TODO: Add timeouts and error checking for safety */
while (!(STM32L_I2C_SR1(port) & (1 << 6)))
while (!(STM32_I2C_SR1(port) & (1 << 6)))
;
}
static void wait_tx(int port)
{
/* TODO: Add timeouts and error checking for safety */
while (!(STM32L_I2C_SR1(port) & (1 << 7)))
while (!(STM32_I2C_SR1(port) & (1 << 7)))
;
}
@@ -73,7 +73,7 @@ static int i2c_read_raw(int port, void *buf, int len)
rx_byte_count = 0;
for (i = 0; i < len; i++) {
wait_rx(port);
data[i] = STM32L_I2C_DR(port);
data[i] = STM32_I2C_DR(port);
rx_byte_count++;
}
mutex_unlock(&port_mutex[port]);
@@ -90,7 +90,7 @@ static int i2c_write_raw(int port, void *buf, int len)
tx_byte_count = 0;
for (i = 0; i < len; i++) {
tx_byte_count++;
STM32L_I2C_DR(port) = data[i];
STM32_I2C_DR(port) = data[i];
wait_tx(port);
}
mutex_unlock(&port_mutex[port]);
@@ -132,14 +132,14 @@ static void i2c_event_handler(int port)
{
/* save and clear status */
i2c_sr1[port] = STM32L_I2C_SR1(port);
STM32L_I2C_SR1(port) = 0;
i2c_sr1[port] = STM32_I2C_SR1(port);
STM32_I2C_SR1(port) = 0;
/* transfer matched our slave address */
if (i2c_sr1[port] & (1 << 1)) {
/* cleared by reading SR1 followed by reading SR2 */
STM32L_I2C_SR1(port);
STM32L_I2C_SR2(port);
STM32_I2C_SR1(port);
STM32_I2C_SR2(port);
#ifdef CONFIG_DEBUG
CPRINTF("%s: ADDR\n", __func__);
#endif
@@ -150,8 +150,8 @@ static void i2c_event_handler(int port)
#endif
} else if (i2c_sr1[port] & (1 << 4)) {
/* clear STOPF bit by reading SR1 and then writing CR1 */
STM32L_I2C_SR1(port);
STM32L_I2C_CR1(port) = STM32L_I2C_CR1(port);
STM32_I2C_SR1(port);
STM32_I2C_CR1(port) = STM32_I2C_CR1(port);
#ifdef CONFIG_DEBUG
CPRINTF("%s: STOPF\n", __func__);
#endif
@@ -169,11 +169,11 @@ static void i2c_event_handler(int port)
}
}
static void i2c2_event_interrupt(void) { i2c_event_handler(I2C2); }
DECLARE_IRQ(STM32L_IRQ_I2C2_EV, i2c2_event_interrupt, 3);
DECLARE_IRQ(STM32_IRQ_I2C2_EV, i2c2_event_interrupt, 3);
static void i2c_error_handler(int port)
{
i2c_sr1[port] = STM32L_I2C_SR1(port);
i2c_sr1[port] = STM32_I2C_SR1(port);
#ifdef CONFIG_DEBUG
if (i2c_sr1[port] & 1 << 10) {
@@ -185,42 +185,42 @@ static void i2c_error_handler(int port)
__func__, tx_byte_count, rx_byte_count);
CPRINTF("%s: I2C_SR1(%s): 0x%04x\n", __func__, port, i2c_sr1[port]);
CPRINTF("%s: I2C_SR2(%s): 0x%04x\n",
__func__, port, STM32L_I2C_SR2(port));
__func__, port, STM32_I2C_SR2(port));
#endif
STM32L_I2C_SR1(port) &= ~0xdf00;
STM32_I2C_SR1(port) &= ~0xdf00;
}
static void i2c2_error_interrupt(void) { i2c_error_handler(I2C2); }
DECLARE_IRQ(STM32L_IRQ_I2C2_ER, i2c2_error_interrupt, 2);
DECLARE_IRQ(STM32_IRQ_I2C2_ER, i2c2_error_interrupt, 2);
static int i2c_init2(void)
{
int i;
/* enable I2C2 clock */
STM32L_RCC_APB1ENR |= 1 << 22;
STM32_RCC_APB1ENR |= 1 << 22;
/* set clock configuration : standard mode (100kHz) */
STM32L_I2C_CCR(I2C2) = I2C_CCR;
STM32_I2C_CCR(I2C2) = I2C_CCR;
/* set slave address */
STM32L_I2C_OAR1(I2C2) = I2C_ADDRESS;
STM32_I2C_OAR1(I2C2) = I2C_ADDRESS;
/* configuration : I2C mode / Periphal enabled, ACK enabled */
STM32L_I2C_CR1(I2C2) = (1 << 10) | (1 << 0);
STM32_I2C_CR1(I2C2) = (1 << 10) | (1 << 0);
/* error and event interrupts enabled / input clock is 16Mhz */
STM32L_I2C_CR2(I2C2) = (1 << 9) | (1 << 8) | 0x10;
STM32_I2C_CR2(I2C2) = (1 << 9) | (1 << 8) | 0x10;
/* clear status */
STM32L_I2C_SR1(I2C2) = 0;
STM32_I2C_SR1(I2C2) = 0;
/* No tasks are waiting on ports */
for (i = 0; i < NUM_PORTS; i++)
task_waiting_on_port[i] = TASK_ID_INVALID;
/* enable event and error interrupts */
task_enable_irq(STM32L_IRQ_I2C2_EV);
task_enable_irq(STM32L_IRQ_I2C2_ER);
task_enable_irq(STM32_IRQ_I2C2_EV);
task_enable_irq(STM32_IRQ_I2C2_ER);
CPUTS("done\n");
return EC_SUCCESS;

2
chip/stm32l/jtag.c → chip/stm32/jtag.c
View File

@@ -10,7 +10,7 @@
int jtag_pre_init(void)
{
/* stop TIM2, TIM3 and watchdogs when the JTAG stops the CPU */
STM32L_DBGMCU_APB1FZ |= 0x00001803;
STM32_DBGMCU_APB1FZ |= 0x00001803;
return EC_SUCCESS;
}

16
chip/stm32l/keyboard_scan.c → chip/stm32/keyboard_scan.c
View File

@@ -115,7 +115,7 @@ static void select_column(int col)
}
if (bsrr)
STM32L_GPIO_BSRR_OFF(ports[i]) = bsrr;
STM32_GPIO_BSRR_OFF(ports[i]) = bsrr;
if (done)
break;
@@ -151,18 +151,18 @@ void wait_for_interrupt(void)
/* Assert all outputs would trigger un-wanted interrupts.
* Clear them before enable interrupt. */
pr_before = STM32L_EXTI_PR;
pr_before = STM32_EXTI_PR;
select_column(COL_ASSERT_ALL);
pr_after = STM32L_EXTI_PR;
STM32L_EXTI_PR |= ((pr_after & ~pr_before) & IRQ_MASK);
pr_after = STM32_EXTI_PR;
STM32_EXTI_PR |= ((pr_after & ~pr_before) & IRQ_MASK);
STM32L_EXTI_IMR |= IRQ_MASK; /* 1: unmask interrupt */
STM32_EXTI_IMR |= IRQ_MASK; /* 1: unmask interrupt */
}
void enter_polling_mode(void)
{
STM32L_EXTI_IMR &= ~IRQ_MASK; /* 0: mask interrupts */
STM32_EXTI_IMR &= ~IRQ_MASK; /* 0: mask interrupts */
select_column(COL_TRI_STATE_ALL);
}
@@ -184,7 +184,7 @@ static int check_keys_changed(void)
r = 0;
#if defined(BOARD_daisy) || defined(BOARD_discovery) || defined(BOARD_adv)
tmp = STM32L_GPIO_IDR(C);
tmp = STM32_GPIO_IDR(C);
/* KB_COL00:04 = PC8:12 */
if (tmp & (1 << 8))
r |= 1 << 0;
@@ -202,7 +202,7 @@ static int check_keys_changed(void)
if (tmp & (1 << 15))
r |= 1 << 6;
tmp = STM32L_GPIO_IDR(D);
tmp = STM32_GPIO_IDR(D);
/* KB_COL07 = PD2 */
if (tmp & (1 << 2))
r |= 1 << 7;

324
chip/stm32/registers.h Normal file
View File

@@ -0,0 +1,324 @@
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Register map for STM32 processor
*/
#ifndef __STM32_REGISTERS
#define __STM32_REGISTERS
#include <stdint.h>
/* concatenation helper */
#define STM32_CAT(prefix, n, suffix) prefix ## n ## suffix
/* Macros to access registers */
#define REG32(addr) (*(volatile uint32_t*)(addr))
#define REG16(addr) (*(volatile uint16_t*)(addr))
/* IRQ numbers */
#define STM32_IRQ_WWDG 0
#define STM32_IRQ_PVD 1
#define STM32_IRQ_TAMPER_STAMP 2
#define STM32_IRQ_RTC_WAKEUP 3
#define STM32_IRQ_FLASH 4
#define STM32_IRQ_RCC 5
#define STM32_IRQ_EXTI0 6
#define STM32_IRQ_EXTI1 7
#define STM32_IRQ_EXTI2 8
#define STM32_IRQ_EXTI3 9
#define STM32_IRQ_EXTI4 10
#define STM32_IRQ_DMA_CHANNEL_1 11
#define STM32_IRQ_DMA_CHANNEL_2 12
#define STM32_IRQ_DMA_CHANNEL_3 13
#define STM32_IRQ_DMA_CHANNEL_4 14
#define STM32_IRQ_DMA_CHANNEL_5 15
#define STM32_IRQ_DMA_CHANNEL_6 16
#define STM32_IRQ_DMA_CHANNEL_7 17
#define STM32_IRQ_ADC_1 18
#define STM32_IRQ_USB_HP 19
#define STM32_IRQ_USB_LP 20
#define STM32_IRQ_DAC 21
#define STM32_IRQ_COMP 22
#define STM32_IRQ_EXTI9_5 23
#define STM32_IRQ_LCD 24
#define STM32_IRQ_TIM9 25
#define STM32_IRQ_TIM10 26
#define STM32_IRQ_TIM11 27
#define STM32_IRQ_TIM2 28
#define STM32_IRQ_TIM3 29
#define STM32_IRQ_TIM4 30
#define STM32_IRQ_I2C1_EV 31
#define STM32_IRQ_I2C1_ER 32
#define STM32_IRQ_I2C2_EV 33
#define STM32_IRQ_I2C2_ER 34
#define STM32_IRQ_SPI1 35
#define STM32_IRQ_SPI2 36
#define STM32_IRQ_USART1 37
#define STM32_IRQ_USART2 38
#define STM32_IRQ_USART3 39
#define STM32_IRQ_EXTI15_10 40
#define STM32_IRQ_RTC_ALARM 41
#define STM32_IRQ_USB_FS_WAKEUP 42
#define STM32_IRQ_TIM6 43
#define STM32_IRQ_TIM7 44
/* --- USART --- */
#define STM32_USART1_BASE 0x40013800
#define STM32_USART2_BASE 0x40004400
#define STM32_USART3_BASE 0x40004800
#define STM32_USART_BASE(n) STM32_CAT(STM32_USART, n, _BASE)
#define STM32_USART_REG(n, offset) \
REG16(STM32_CAT(STM32_USART, n, _BASE) + (offset))
#define STM32_USART_SR(n) STM32_USART_REG(n, 0x00)
#define STM32_USART_DR(n) STM32_USART_REG(n, 0x04)
#define STM32_USART_BRR(n) STM32_USART_REG(n, 0x08)
#define STM32_USART_CR1(n) STM32_USART_REG(n, 0x0C)
#define STM32_USART_CR2(n) STM32_USART_REG(n, 0x10)
#define STM32_USART_CR3(n) STM32_USART_REG(n, 0x14)
#define STM32_USART_GTPR(n) STM32_USART_REG(n, 0x18)
#define STM32_IRQ_USART(n) STM32_CAT(STM32_IRQ_USART, n, )
/* --- TIMERS --- */
#define STM32_TIM2_BASE 0x40000000
#define STM32_TIM3_BASE 0x40000400
#define STM32_TIM4_BASE 0x40000800
#define STM32_TIM6_BASE 0x40001000
#define STM32_TIM7_BASE 0x40001400
#define STM32_TIM9_BASE 0x40010800
#define STM32_TIM10_BASE 0x40010C00
#define STM32_TIM11_BASE 0x40011000
#define STM32_TIM_REG(n, offset) \
REG16(STM32_CAT(STM32_TIM, n, _BASE) + (offset))
#define STM32_TIM_CR1(n) STM32_TIM_REG(n, 0x00)
#define STM32_TIM_CR2(n) STM32_TIM_REG(n, 0x04)
#define STM32_TIM_SMCR(n) STM32_TIM_REG(n, 0x08)
#define STM32_TIM_DIER(n) STM32_TIM_REG(n, 0x0C)
#define STM32_TIM_SR(n) STM32_TIM_REG(n, 0x10)
#define STM32_TIM_EGR(n) STM32_TIM_REG(n, 0x14)
#define STM32_TIM_CCMR1(n) STM32_TIM_REG(n, 0x18)
#define STM32_TIM_CCMR2(n) STM32_TIM_REG(n, 0x1C)
#define STM32_TIM_CCER(n) STM32_TIM_REG(n, 0x20)
#define STM32_TIM_CNT(n) STM32_TIM_REG(n, 0x24)
#define STM32_TIM_PSC(n) STM32_TIM_REG(n, 0x28)
#define STM32_TIM_ARR(n) STM32_TIM_REG(n, 0x2C)
#define STM32_TIM_CCR1(n) STM32_TIM_REG(n, 0x34)
#define STM32_TIM_CCR2(n) STM32_TIM_REG(n, 0x38)
#define STM32_TIM_CCR3(n) STM32_TIM_REG(n, 0x3C)
#define STM32_TIM_CCR4(n) STM32_TIM_REG(n, 0x40)
#define STM32_TIM_DCR(n) STM32_TIM_REG(n, 0x48)
#define STM32_TIM_DMAR(n) STM32_TIM_REG(n, 0x4C)
#define STM32_TIM_OR(n) STM32_TIM_REG(n, 0x50)
/* --- GPIO --- */
#define STM32_GPIOA_BASE 0x40020000
#define STM32_GPIOB_BASE 0x40020400
#define STM32_GPIOC_BASE 0x40020800
#define STM32_GPIOD_BASE 0x40020C00
#define STM32_GPIOE_BASE 0x40021000
#define STM32_GPIOH_BASE 0x40021400
#define GPIO_A STM32_GPIOA_BASE
#define GPIO_B STM32_GPIOB_BASE
#define GPIO_C STM32_GPIOC_BASE
#define GPIO_D STM32_GPIOD_BASE
#define GPIO_E STM32_GPIOE_BASE
#define GPIO_H STM32_GPIOH_BASE
#define STM32_GPIO_REG32(l, offset) \
REG32(STM32_CAT(STM32_GPIO, l, _BASE) + (offset))
#define STM32_GPIO_REG16(l, offset) \
REG16(STM32_CAT(STM32_GPIO, l, _BASE) + (offset))
#define STM32_GPIO_MODER(l) STM32_GPIO_REG32(l, 0x00)
#define STM32_GPIO_OTYPER(l) STM32_GPIO_REG16(l, 0x04)
#define STM32_GPIO_OSPEEDR(l) STM32_GPIO_REG32(l, 0x08)
#define STM32_GPIO_PUPDR(l) STM32_GPIO_REG32(l, 0x0C)
#define STM32_GPIO_IDR(l) STM32_GPIO_REG16(l, 0x10)
#define STM32_GPIO_ODR(l) STM32_GPIO_REG16(l, 0x14)
#define STM32_GPIO_BSRR(l) STM32_GPIO_REG32(l, 0x18)
#define STM32_GPIO_LCKR(l) STM32_GPIO_REG32(l, 0x1C)
#define STM32_GPIO_AFRL(l) STM32_GPIO_REG32(l, 0x20)
#define STM32_GPIO_AFRH(l) STM32_GPIO_REG32(l, 0x24)
#define STM32_GPIO_MODER_OFF(b) REG32((b) + 0x00)
#define STM32_GPIO_OTYPER_OFF(b) REG16((b) + 0x04)
#define STM32_GPIO_OSPEEDR_OFF(b) REG32((b) + 0x08)
#define STM32_GPIO_PUPDR_OFF(b) REG32((b) + 0x0C)
#define STM32_GPIO_IDR_OFF(b) REG16((b) + 0x10)
#define STM32_GPIO_ODR_OFF(b) REG16((b) + 0x14)
#define STM32_GPIO_BSRR_OFF(b) REG32((b) + 0x18)
#define STM32_GPIO_LCKR_OFF(b) REG32((b) + 0x1C)
#define STM32_GPIO_AFRL_OFF(b) REG32((b) + 0x20)
#define STM32_GPIO_AFRH_OFF(b) REG32((b) + 0x24)
#define GPIO_ALT_SYS 0x0
#define GPIO_ALT_TIM2 0x1
#define GPIO_ALT_TIM3_4 0x2
#define GPIO_ALT_TIM9_11 0x3
#define GPIO_ALT_I2C 0x4
#define GPIO_ALT_SPI 0x5
#define GPIO_ALT_USART 0x7
#define GPIO_ALT_USB 0xA
#define GPIO_ALT_LCD 0xB
#define GPIO_ALT_RI 0xE
#define GPIO_ALT_EVENTOUT 0xF
/* --- I2C --- */
#define STM32_I2C1_BASE 0x40005400
#define STM32_I2C2_BASE 0x40005800
#define STM32_I2C1_PORT 0
#define STM32_I2C2_PORT 1
static inline uint16_t *stm32_i2c_reg(int port, int offset)
{
return (uint16_t *)((STM32_I2C1_BASE + (port * 0x400)) + offset);
}
#define STM32_I2C_CR1(n) REG16(stm32_i2c_reg(n, 0x00))
#define STM32_I2C_CR2(n) REG16(stm32_i2c_reg(n, 0x04))
#define STM32_I2C_OAR1(n) REG16(stm32_i2c_reg(n, 0x08))
#define STM32_I2C_OAR2(n) REG16(stm32_i2c_reg(n, 0x0C))
#define STM32_I2C_DR(n) REG16(stm32_i2c_reg(n, 0x10))
#define STM32_I2C_SR1(n) REG16(stm32_i2c_reg(n, 0x14))
#define STM32_I2C_SR2(n) REG16(stm32_i2c_reg(n, 0x18))
#define STM32_I2C_CCR(n) REG16(stm32_i2c_reg(n, 0x1C))
#define STM32_I2C_TRISE(n) REG16(stm32_i2c_reg(n, 0x20))
/* --- Power / Reset / Clocks --- */
#define STM32_PWR_BASE 0x40007000
#define STM32_PWR_CR REG32(STM32_PWR_BASE + 0x00)
#define STM32_PWR_CSR REG32(STM32_PWR_BASE + 0x04)
#define STM32_RCC_BASE 0x40023800
#define STM32_RCC_CR REG32(STM32_RCC_BASE + 0x00)
#define STM32_RCC_ICSR REG32(STM32_RCC_BASE + 0x04)
#define STM32_RCC_CFGR REG32(STM32_RCC_BASE + 0x08)
#define STM32_RCC_CIR REG32(STM32_RCC_BASE + 0x0C)
#define STM32_RCC_AHBRSTR REG32(STM32_RCC_BASE + 0x10)
#define STM32_RCC_APB2RSTR REG32(STM32_RCC_BASE + 0x14)
#define STM32_RCC_APB1RSTR REG32(STM32_RCC_BASE + 0x18)
#define STM32_RCC_AHBENR REG32(STM32_RCC_BASE + 0x1C)
#define STM32_RCC_APB2ENR REG32(STM32_RCC_BASE + 0x20)
#define STM32_RCC_APB1ENR REG32(STM32_RCC_BASE + 0x24)
#define STM32_RCC_AHBLPENR REG32(STM32_RCC_BASE + 0x28)
#define STM32_RCC_APB2LPENR REG32(STM32_RCC_BASE + 0x2C)
#define STM32_RCC_APB1LPENR REG32(STM32_RCC_BASE + 0x30)
#define STM32_RCC_CSR REG32(STM32_RCC_BASE + 0x34)
#define STM32_SYSCFG_BASE 0x40010000
#define STM32_SYSCFG_MEMRMP REG32(STM32_SYSCFG_BASE + 0x00)
#define STM32_SYSCFG_PMC REG32(STM32_SYSCFG_BASE + 0x04)
#define STM32_SYSCFG_EXTICR(n) REG32(STM32_SYSCFG_BASE + 8 + 4 * (n))
/* --- Watchdogs --- */
#define STM32_WWDG_BASE 0x40002C00
#define STM32_WWDG_CR REG32(STM32_WWDG_BASE + 0x00)
#define STM32_WWDG_CFR REG32(STM32_WWDG_BASE + 0x04)
#define STM32_WWDG_SR REG32(STM32_WWDG_BASE + 0x08)
#define STM32_IWDG_BASE 0x40003000
#define STM32_IWDG_KR REG32(STM32_IWDG_BASE + 0x00)
#define STM32_IWDG_PR REG32(STM32_IWDG_BASE + 0x04)
#define STM32_IWDG_RLR REG32(STM32_IWDG_BASE + 0x08)
#define STM32_IWDG_SR REG32(STM32_IWDG_BASE + 0x0C)
/* --- Real-Time Clock --- */
#define STM32_RTC_BASE 0x40002800
#define STM32_RTC_TR REG32(STM32_RTC_BASE + 0x00)
#define STM32_RTC_DR REG32(STM32_RTC_BASE + 0x04)
#define STM32_RTC_CR REG32(STM32_RTC_BASE + 0x08)
#define STM32_RTC_ISR REG32(STM32_RTC_BASE + 0x0C)
#define STM32_RTC_PRER REG32(STM32_RTC_BASE + 0x10)
#define STM32_RTC_WUTR REG32(STM32_RTC_BASE + 0x14)
#define STM32_RTC_CALIBR REG32(STM32_RTC_BASE + 0x18)
#define STM32_RTC_ALRMAR REG32(STM32_RTC_BASE + 0x1C)
#define STM32_RTC_ALRMBR REG32(STM32_RTC_BASE + 0x20)
#define STM32_RTC_WPR REG32(STM32_RTC_BASE + 0x24)
#define STM32_RTC_TSTR REG32(STM32_RTC_BASE + 0x30)
#define STM32_RTC_TSDR REG32(STM32_RTC_BASE + 0x34)
#define STM32_RTC_TAFCR REG32(STM32_RTC_BASE + 0x40)
#define STM32_RTC_BACKUP(n) REG32(STM32_RTC_BASE + 0x50 + 4 * (n))
/* --- SPI --- */
#define STM32_SPI1_BASE 0x40013000
#define STM32_SPI2_BASE 0x40003800
#define STM32_SPI1_PORT 0
#define STM32_SPI2_PORT 1
/*
* TODO(vpalatin):
* For whatever reason, our toolchain is substandard and generate a
* function every time you are using this inline function.
*
* That's why I have not used inline stuff in the registers definition.
*/
#define stm32_spi_addr(port, offset) \
((port == 0) ? \
(STM32_SPI1_BASE + offset) : \
(STM32_SPI2_BASE + offset))
#define STM32_SPI_REG16(p, l) REG16(stm32_spi_addr((p), l))
#define STM32_SPI_CR1(p) STM32_SPI_REG16((p), 0x00)
#define STM32_SPI_CR2(p) STM32_SPI_REG16((p), 0x04)
#define STM32_SPI_SR(p) STM32_SPI_REG16((p), 0x08)
#define STM32_SPI_DR(p) STM32_SPI_REG16((p), 0x0c)
#define STM32_SPI_CRCPR(p) STM32_SPI_REG16((p), 0x10)
#define STM32_SPI_RXCRCR(p) STM32_SPI_REG16((p), 0x14)
#define STM32_SPI_TXCRCR(p) STM32_SPI_REG16((p), 0x18)
/* --- Debug --- */
#define STM32_DBGMCU_BASE 0xE0042000
#define STM32_DBGMCU_IDCODE REG32(STM32_DBGMCU_BASE + 0x00)
#define STM32_DBGMCU_CR REG32(STM32_DBGMCU_BASE + 0x04)
#define STM32_DBGMCU_APB1FZ REG32(STM32_DBGMCU_BASE + 0x08)
#define STM32_DBGMCU_APB2FZ REG32(STM32_DBGMCU_BASE + 0x0C)
/* --- Flash --- */
#define STM32_FLASH_REGS_BASE 0x40023c00
#define STM32_FLASH_ACR REG32(STM32_FLASH_REGS_BASE + 0x00)
/* --- External Interrupts --- */
#define STM32_EXTI_BASE 0x40010400
#define STM32_EXTI_IMR REG32(STM32_EXTI_BASE + 0x00)
#define STM32_EXTI_EMR REG32(STM32_EXTI_BASE + 0x04)
#define STM32_EXTI_RTSR REG32(STM32_EXTI_BASE + 0x08)
#define STM32_EXTI_FTSR REG32(STM32_EXTI_BASE + 0x0c)
#define STM32_EXTI_SWIER REG32(STM32_EXTI_BASE + 0x10)
#define STM32_EXTI_PR REG32(STM32_EXTI_BASE + 0x14)
/* --- MISC --- */
#define STM32_RI_BASE 0x40007C04
#define STM32_ADC1_BASE 0x40012400
#define STM32_ADC_BASE 0x40012700
#define STM32_COMP_BASE 0x40007C00
#define STM32_DAC_BASE 0x40007400
#define STM32_CRC_BASE 0x40023000
#define STM32_LCD_BASE 0x40002400
#define STM32_DMA1_BASE 0x40026000
#define STM32_DMA2_BASE 0x40026400
#endif /* __STM32_REGISTERS */

34
chip/stm32l/spi.c → chip/stm32/spi.c
View File

@@ -51,7 +51,7 @@ static char in_msg[32 + MSG_PROTO_BYTES];
*/
void spi_work_task(void)
{
int port = STM32L_SPI1_PORT;
int port = STM32_SPI1_PORT;
while (1) {
task_wait_event(-1);
@@ -63,8 +63,8 @@ void spi_work_task(void)
/* Transfer is now complete, so reset everything */
dma_disable(DMA_CHANNEL_FOR_SPI_RX(port));
dma_disable(DMA_CHANNEL_FOR_SPI_TX(port));
STM32L_SPI_CR2(port) &= ~CR2_TXDMAEN;
STM32L_SPI_DR(port) = 0xff;
STM32_SPI_CR2(port) &= ~CR2_TXDMAEN;
STM32_SPI_DR(port) = 0xff;
}
}
@@ -85,7 +85,7 @@ void spi_work_task(void)
* It is interesting to note that it seems to be possible to run the SPI
* interface faster than the CPU clock with this approach.
*
* @param port Port to send reply back on (STM32L_SPI0/1_PORT)
* @param port Port to send reply back on (STM32_SPI0/1_PORT)
* @param msg Message to send
* @param msg_len Length of message in bytes
*/
@@ -99,9 +99,9 @@ static void reply(int port, char *msg, int msg_len)
* the message, and then a third to do the trailer, rather than
* copying the message around.
*/
STM32L_SPI_CR2(port) |= CR2_TXDMAEN;
STM32_SPI_CR2(port) |= CR2_TXDMAEN;
dmac = DMA_CHANNEL_FOR_SPI_TX(port);
dma_start_tx(dmac, msg_len, (void *)&STM32L_SPI_DR(port), out_msg);
dma_start_tx(dmac, msg_len, (void *)&STM32_SPI_DR(port), out_msg);
}
/**
@@ -113,7 +113,7 @@ static void reply(int port, char *msg, int msg_len)
* We will not get interrupts on subsequent bytes since the DMA will handle
* the incoming data.
*
* @param port Port that the interrupt came in on (STM32L_SPI0/1_PORT)
* @param port Port that the interrupt came in on (STM32_SPI0/1_PORT)
*/
static void spi_interrupt(int port)
{
@@ -123,15 +123,15 @@ static void spi_interrupt(int port)
int cmd;
/* Make sure there is a byte available */
if (!(STM32L_SPI_SR(port) & SR_RXNE))
if (!(STM32_SPI_SR(port) & SR_RXNE))
return;
/* Get the command byte */
cmd = STM32L_SPI_DR(port);
cmd = STM32_SPI_DR(port);
/* Read the rest of the message - for now we do nothing with it */
dmac = DMA_CHANNEL_FOR_SPI_RX(port);
dma_start_rx(dmac, sizeof(in_msg), (void *)&STM32L_SPI_DR(port),
dma_start_rx(dmac, sizeof(in_msg), (void *)&STM32_SPI_DR(port),
in_msg);
/*
@@ -149,9 +149,9 @@ static void spi_interrupt(int port)
}
/* The interrupt code cannot pass a parameters, so handle this here */
static void spi1_interrupt(void) { spi_interrupt(STM32L_SPI1_PORT); };
static void spi1_interrupt(void) { spi_interrupt(STM32_SPI1_PORT); };
DECLARE_IRQ(STM32L_IRQ_SPI1, spi1_interrupt, 2);
DECLARE_IRQ(STM32_IRQ_SPI1, spi1_interrupt, 2);
static int spi_init(void)
{
@@ -167,19 +167,19 @@ static int spi_init(void)
*
* 8-bit data, master mode, full-duplex, clock is fpclk / 2
*/
port = STM32L_SPI1_PORT;
port = STM32_SPI1_PORT;
/* enable rx buffer not empty interrupt, and rx DMA */
STM32L_SPI_CR2(port) |= CR2_RXNEIE | CR2_RXDMAEN;
STM32_SPI_CR2(port) |= CR2_RXNEIE | CR2_RXDMAEN;
/* set up an interrupt when we get the first byte of a packet */
task_enable_irq(STM32L_IRQ_SPI1);
task_enable_irq(STM32_IRQ_SPI1);
/* write 0xff which will be our default output value */
STM32L_SPI_DR(port) = 0xff;
STM32_SPI_DR(port) = 0xff;
/* enable the SPI peripheral */
STM32L_SPI_CR1(port) |= CR1_SPE;
STM32_SPI_CR1(port) |= CR1_SPE;
#else
#error "Need to know how to set up SPI for this board"
#endif

22
chip/stm32l/system.c → chip/stm32/system.c
View File

@@ -14,10 +14,10 @@ static void check_reset_cause(void)
{
enum system_image_copy_t copy = system_get_image_copy();
enum system_reset_cause_t reset_cause = SYSTEM_RESET_UNKNOWN;
uint32_t raw_cause = STM32L_RCC_CSR;
uint32_t raw_cause = STM32_RCC_CSR;
/* Clear the hardware reset cause by setting the RMVF bit */
STM32L_RCC_CSR |= 1 << 24;
STM32_RCC_CSR |= 1 << 24;
if (copy == SYSTEM_IMAGE_RW_A || copy == SYSTEM_IMAGE_RW_B) {
/* If we're in image A or B, the only way we can get there is
@@ -52,21 +52,21 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
int system_pre_init(void)
{
/* enable clock on Power module */
STM32L_RCC_APB1ENR |= 1 << 28;
STM32_RCC_APB1ENR |= 1 << 28;
/* Enable access to RCC CSR register and RTC backup registers */
STM32L_PWR_CR |= 1 << 8;
STM32_PWR_CR |= 1 << 8;
/* switch on LSI */
STM32L_RCC_CSR |= 1 << 0;
STM32_RCC_CSR |= 1 << 0;
/* Wait for LSI to be ready */
while (!(STM32L_RCC_CSR & (1 << 1)))
while (!(STM32_RCC_CSR & (1 << 1)))
;
/* re-configure RTC if needed */
if ((STM32L_RCC_CSR & 0x00C30000) != 0x00420000) {
if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
/* the RTC settings are bad, we need to reset it */
STM32L_RCC_CSR |= 0x00800000;
STM32_RCC_CSR |= 0x00800000;
/* Enable RTC and use LSI as clock source */
STM32L_RCC_CSR = (STM32L_RCC_CSR & ~0x00C30000) | 0x00420000;
STM32_RCC_CSR = (STM32_RCC_CSR & ~0x00C30000) | 0x00420000;
}
check_reset_cause();
@@ -93,7 +93,7 @@ int system_reset(int is_cold)
int system_set_scratchpad(uint32_t value)
{
STM32L_RTC_BACKUP(0) = value;
STM32_RTC_BACKUP(0) = value;
return EC_SUCCESS;
}
@@ -101,7 +101,7 @@ int system_set_scratchpad(uint32_t value)
uint32_t system_get_scratchpad(void)
{
return STM32L_RTC_BACKUP(0);
return STM32_RTC_BACKUP(0);
}

46
chip/stm32l/uart.c → chip/stm32/uart.c
View File

@@ -31,36 +31,36 @@ int uart_init_done(void)
void uart_tx_start(void)
{
STM32L_USART_CR1(UARTN) |= 0x80;
STM32_USART_CR1(UARTN) |= 0x80;
should_stop = 0;
task_trigger_irq(STM32L_IRQ_USART(UARTN));
task_trigger_irq(STM32_IRQ_USART(UARTN));
}
void uart_tx_stop(void)
{
STM32L_USART_CR1(UARTN) &= ~0x80;
STM32_USART_CR1(UARTN) &= ~0x80;
should_stop = 1;
}
int uart_tx_stopped(void)
{
return !(STM32L_USART_CR1(UARTN) & 0x80);
return !(STM32_USART_CR1(UARTN) & 0x80);
}
void uart_tx_flush(void)
{
while (!(STM32L_USART_SR(UARTN) & 0x80))
while (!(STM32_USART_SR(UARTN) & 0x80))
;
}
int uart_tx_ready(void)
{
return STM32L_USART_SR(UARTN) & 0x80;
return STM32_USART_SR(UARTN) & 0x80;
}
int uart_rx_available(void)
{
return STM32L_USART_SR(UARTN) & 0x20;
return STM32_USART_SR(UARTN) & 0x20;
}
void uart_write_char(char c)
@@ -70,22 +70,22 @@ void uart_write_char(char c)
* before a line feed in the interrupt routine.
*/
while (!uart_tx_ready()) ;
STM32L_USART_DR(UARTN) = c;
STM32_USART_DR(UARTN) = c;
}
int uart_read_char(void)
{
return STM32L_USART_DR(UARTN);
return STM32_USART_DR(UARTN);
}
void uart_disable_interrupt(void)
{
task_disable_irq(STM32L_IRQ_USART(UARTN));
task_disable_irq(STM32_IRQ_USART(UARTN));
}
void uart_enable_interrupt(void)
{
task_enable_irq(STM32L_IRQ_USART(UARTN));
task_enable_irq(STM32_IRQ_USART(UARTN));
}
/* Interrupt handler for console USART */
@@ -95,7 +95,7 @@ static void uart_interrupt(void)
* Disable the TX empty interrupt before filling the TX buffer since it
* needs an actual write to DR to be cleared.
*/
STM32L_USART_CR1(UARTN) &= ~0x80;
STM32_USART_CR1(UARTN) &= ~0x80;
/* Read input FIFO until empty, then fill output FIFO */
uart_process();
@@ -105,9 +105,9 @@ static void uart_interrupt(void)
* uart_process.
*/
if (!should_stop)
STM32L_USART_CR1(UARTN) |= 0x80;
STM32_USART_CR1(UARTN) |= 0x80;
}
DECLARE_IRQ(STM32L_IRQ_USART(UARTN), uart_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_USART(UARTN), uart_interrupt, 1);
int uart_init(void)
{
@@ -115,34 +115,34 @@ int uart_init(void)
* Check that the UART parameters used for panic/watchdog are matching
* the console USART parameters.
*/
BUILD_ASSERT(STM32L_USART_BASE(UARTN) == CONFIG_UART_ADDRESS);
BUILD_ASSERT(STM32_USART_BASE(UARTN) == CONFIG_UART_ADDRESS);
/* Enable USART clock */
if (UARTN == 1)
STM32L_RCC_APB2ENR |= 1 << 14; /* USART1 */
STM32_RCC_APB2ENR |= 1 << 14; /* USART1 */
else if (UARTN == 2)
STM32L_RCC_APB1ENR |= 1 << 17; /* USART2 */
STM32_RCC_APB1ENR |= 1 << 17; /* USART2 */
else if (UARTN == 3)
STM32L_RCC_APB1ENR |= 1 << 18; /* USART3 */
STM32_RCC_APB1ENR |= 1 << 18; /* USART3 */
/* UART enabled, 8 Data bits, oversampling x16, no parity,
* RXNE interrupt, TX and RX enabled.
*/
STM32L_USART_CR1(UARTN) = 0x202C;
STM32_USART_CR1(UARTN) = 0x202C;
/* 1 stop bit, no fancy stuff */
STM32L_USART_CR2(UARTN) = 0x0000;
STM32_USART_CR2(UARTN) = 0x0000;
/* DMA disabled, special modes disabled, error interrupt disabled */
STM32L_USART_CR3(UARTN) = 0x0000;
STM32_USART_CR3(UARTN) = 0x0000;
/* Select the baud rate
* using x16 oversampling (OVER8 == 0)
*/
STM32L_USART_BRR(UARTN) = DIV_ROUND_NEAREST(CPU_CLOCK, BAUD_RATE);
STM32_USART_BRR(UARTN) = DIV_ROUND_NEAREST(CPU_CLOCK, BAUD_RATE);
/* Enable interrupts */
task_enable_irq(STM32L_IRQ_USART(UARTN));
task_enable_irq(STM32_IRQ_USART(UARTN));
init_done = 1;

10
chip/stm32l/watchdog.c → chip/stm32/watchdog.c
View File

@@ -29,7 +29,7 @@
void watchdog_reload(void)
{
/* Reload the watchdog */
STM32L_IWDG_KR = 0xaaaa;
STM32_IWDG_KR = 0xaaaa;
}
@@ -41,15 +41,15 @@ int watchdog_init(int period_ms)
watchdog_period = period_ms * (LSI_CLOCK / IWDG_PRESCALER_DIV) / 1000;
/* Unlock watchdog registers */
STM32L_IWDG_KR = 0x5555;
STM32_IWDG_KR = 0x5555;
/* Set the prescaler between the LSI clock and the watchdog counter */
STM32L_IWDG_PR = IWDG_PRESCALER & 7;
STM32_IWDG_PR = IWDG_PRESCALER & 7;
/* Set the reload value of the watchdog counter */
STM32L_IWDG_RLR = watchdog_period & 0x7FF ;
STM32_IWDG_RLR = watchdog_period & 0x7FF ;
/* Start the watchdog (and re-lock registers) */
STM32L_IWDG_KR = 0xcccc;
STM32_IWDG_KR = 0xcccc;
return EC_SUCCESS;
}

324
chip/stm32l/registers.h
View File

@@ -1,324 +0,0 @@
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Register map for STM32L processor
*/
#ifndef __STM32L_REGISTERS
#define __STM32L_REGISTERS
#include <stdint.h>
/* concatenation helper */
#define STM32L_CAT(prefix, n, suffix) prefix ## n ## suffix
/* Macros to access registers */
#define REG32(addr) (*(volatile uint32_t*)(addr))
#define REG16(addr) (*(volatile uint16_t*)(addr))
/* IRQ numbers */
#define STM32L_IRQ_WWDG 0
#define STM32L_IRQ_PVD 1
#define STM32L_IRQ_TAMPER_STAMP 2
#define STM32L_IRQ_RTC_WAKEUP 3
#define STM32L_IRQ_FLASH 4
#define STM32L_IRQ_RCC 5
#define STM32L_IRQ_EXTI0 6
#define STM32L_IRQ_EXTI1 7
#define STM32L_IRQ_EXTI2 8
#define STM32L_IRQ_EXTI3 9
#define STM32L_IRQ_EXTI4 10
#define STM32L_IRQ_DMA_CHANNEL_1 11
#define STM32L_IRQ_DMA_CHANNEL_2 12
#define STM32L_IRQ_DMA_CHANNEL_3 13
#define STM32L_IRQ_DMA_CHANNEL_4 14
#define STM32L_IRQ_DMA_CHANNEL_5 15
#define STM32L_IRQ_DMA_CHANNEL_6 16
#define STM32L_IRQ_DMA_CHANNEL_7 17
#define STM32L_IRQ_ADC_1 18
#define STM32L_IRQ_USB_HP 19
#define STM32L_IRQ_USB_LP 20
#define STM32L_IRQ_DAC 21
#define STM32L_IRQ_COMP 22
#define STM32L_IRQ_EXTI9_5 23
#define STM32L_IRQ_LCD 24
#define STM32L_IRQ_TIM9 25
#define STM32L_IRQ_TIM10 26
#define STM32L_IRQ_TIM11 27
#define STM32L_IRQ_TIM2 28
#define STM32L_IRQ_TIM3 29
#define STM32L_IRQ_TIM4 30
#define STM32L_IRQ_I2C1_EV 31
#define STM32L_IRQ_I2C1_ER 32
#define STM32L_IRQ_I2C2_EV 33
#define STM32L_IRQ_I2C2_ER 34
#define STM32L_IRQ_SPI1 35
#define STM32L_IRQ_SPI2 36
#define STM32L_IRQ_USART1 37
#define STM32L_IRQ_USART2 38
#define STM32L_IRQ_USART3 39
#define STM32L_IRQ_EXTI15_10 40
#define STM32L_IRQ_RTC_ALARM 41
#define STM32L_IRQ_USB_FS_WAKEUP 42
#define STM32L_IRQ_TIM6 43
#define STM32L_IRQ_TIM7 44
/* --- USART --- */
#define STM32L_USART1_BASE 0x40013800
#define STM32L_USART2_BASE 0x40004400
#define STM32L_USART3_BASE 0x40004800
#define STM32L_USART_BASE(n) STM32L_CAT(STM32L_USART, n, _BASE)
#define STM32L_USART_REG(n, offset) \
REG16(STM32L_CAT(STM32L_USART, n, _BASE) + (offset))
#define STM32L_USART_SR(n) STM32L_USART_REG(n, 0x00)
#define STM32L_USART_DR(n) STM32L_USART_REG(n, 0x04)
#define STM32L_USART_BRR(n) STM32L_USART_REG(n, 0x08)
#define STM32L_USART_CR1(n) STM32L_USART_REG(n, 0x0C)
#define STM32L_USART_CR2(n) STM32L_USART_REG(n, 0x10)
#define STM32L_USART_CR3(n) STM32L_USART_REG(n, 0x14)
#define STM32L_USART_GTPR(n) STM32L_USART_REG(n, 0x18)
#define STM32L_IRQ_USART(n) STM32L_CAT(STM32L_IRQ_USART, n, )
/* --- TIMERS --- */
#define STM32L_TIM2_BASE 0x40000000
#define STM32L_TIM3_BASE 0x40000400
#define STM32L_TIM4_BASE 0x40000800
#define STM32L_TIM6_BASE 0x40001000
#define STM32L_TIM7_BASE 0x40001400
#define STM32L_TIM9_BASE 0x40010800
#define STM32L_TIM10_BASE 0x40010C00
#define STM32L_TIM11_BASE 0x40011000
#define STM32L_TIM_REG(n, offset) \
REG16(STM32L_CAT(STM32L_TIM, n, _BASE) + (offset))
#define STM32L_TIM_CR1(n) STM32L_TIM_REG(n, 0x00)
#define STM32L_TIM_CR2(n) STM32L_TIM_REG(n, 0x04)
#define STM32L_TIM_SMCR(n) STM32L_TIM_REG(n, 0x08)
#define STM32L_TIM_DIER(n) STM32L_TIM_REG(n, 0x0C)
#define STM32L_TIM_SR(n) STM32L_TIM_REG(n, 0x10)
#define STM32L_TIM_EGR(n) STM32L_TIM_REG(n, 0x14)
#define STM32L_TIM_CCMR1(n) STM32L_TIM_REG(n, 0x18)
#define STM32L_TIM_CCMR2(n) STM32L_TIM_REG(n, 0x1C)
#define STM32L_TIM_CCER(n) STM32L_TIM_REG(n, 0x20)
#define STM32L_TIM_CNT(n) STM32L_TIM_REG(n, 0x24)
#define STM32L_TIM_PSC(n) STM32L_TIM_REG(n, 0x28)
#define STM32L_TIM_ARR(n) STM32L_TIM_REG(n, 0x2C)
#define STM32L_TIM_CCR1(n) STM32L_TIM_REG(n, 0x34)
#define STM32L_TIM_CCR2(n) STM32L_TIM_REG(n, 0x38)
#define STM32L_TIM_CCR3(n) STM32L_TIM_REG(n, 0x3C)
#define STM32L_TIM_CCR4(n) STM32L_TIM_REG(n, 0x40)
#define STM32L_TIM_DCR(n) STM32L_TIM_REG(n, 0x48)
#define STM32L_TIM_DMAR(n) STM32L_TIM_REG(n, 0x4C)
#define STM32L_TIM_OR(n) STM32L_TIM_REG(n, 0x50)
/* --- GPIO --- */
#define STM32L_GPIOA_BASE 0x40020000
#define STM32L_GPIOB_BASE 0x40020400
#define STM32L_GPIOC_BASE 0x40020800
#define STM32L_GPIOD_BASE 0x40020C00
#define STM32L_GPIOE_BASE 0x40021000
#define STM32L_GPIOH_BASE 0x40021400
#define GPIO_A STM32L_GPIOA_BASE
#define GPIO_B STM32L_GPIOB_BASE
#define GPIO_C STM32L_GPIOC_BASE
#define GPIO_D STM32L_GPIOD_BASE
#define GPIO_E STM32L_GPIOE_BASE
#define GPIO_H STM32L_GPIOH_BASE
#define STM32L_GPIO_REG32(l, offset) \
REG32(STM32L_CAT(STM32L_GPIO, l, _BASE) + (offset))
#define STM32L_GPIO_REG16(l, offset) \
REG16(STM32L_CAT(STM32L_GPIO, l, _BASE) + (offset))
#define STM32L_GPIO_MODER(l) STM32L_GPIO_REG32(l, 0x00)
#define STM32L_GPIO_OTYPER(l) STM32L_GPIO_REG16(l, 0x04)
#define STM32L_GPIO_OSPEEDR(l) STM32L_GPIO_REG32(l, 0x08)
#define STM32L_GPIO_PUPDR(l) STM32L_GPIO_REG32(l, 0x0C)
#define STM32L_GPIO_IDR(l) STM32L_GPIO_REG16(l, 0x10)
#define STM32L_GPIO_ODR(l) STM32L_GPIO_REG16(l, 0x14)
#define STM32L_GPIO_BSRR(l) STM32L_GPIO_REG32(l, 0x18)
#define STM32L_GPIO_LCKR(l) STM32L_GPIO_REG32(l, 0x1C)
#define STM32L_GPIO_AFRL(l) STM32L_GPIO_REG32(l, 0x20)
#define STM32L_GPIO_AFRH(l) STM32L_GPIO_REG32(l, 0x24)
#define STM32L_GPIO_MODER_OFF(b) REG32((b) + 0x00)
#define STM32L_GPIO_OTYPER_OFF(b) REG16((b) + 0x04)
#define STM32L_GPIO_OSPEEDR_OFF(b) REG32((b) + 0x08)
#define STM32L_GPIO_PUPDR_OFF(b) REG32((b) + 0x0C)
#define STM32L_GPIO_IDR_OFF(b) REG16((b) + 0x10)
#define STM32L_GPIO_ODR_OFF(b) REG16((b) + 0x14)
#define STM32L_GPIO_BSRR_OFF(b) REG32((b) + 0x18)
#define STM32L_GPIO_LCKR_OFF(b) REG32((b) + 0x1C)
#define STM32L_GPIO_AFRL_OFF(b) REG32((b) + 0x20)
#define STM32L_GPIO_AFRH_OFF(b) REG32((b) + 0x24)
#define GPIO_ALT_SYS 0x0
#define GPIO_ALT_TIM2 0x1
#define GPIO_ALT_TIM3_4 0x2
#define GPIO_ALT_TIM9_11 0x3
#define GPIO_ALT_I2C 0x4
#define GPIO_ALT_SPI 0x5
#define GPIO_ALT_USART 0x7
#define GPIO_ALT_USB 0xA
#define GPIO_ALT_LCD 0xB
#define GPIO_ALT_RI 0xE
#define GPIO_ALT_EVENTOUT 0xF
/* --- I2C --- */
#define STM32L_I2C1_BASE 0x40005400
#define STM32L_I2C2_BASE 0x40005800
#define STM32L_I2C1_PORT 0
#define STM32L_I2C2_PORT 1
static inline uint16_t *stm32l_i2c_reg(int port, int offset)
{
return (uint16_t *)((STM32L_I2C1_BASE + (port * 0x400)) + offset);
}
#define STM32L_I2C_CR1(n) REG16(stm32l_i2c_reg(n, 0x00))
#define STM32L_I2C_CR2(n) REG16(stm32l_i2c_reg(n, 0x04))
#define STM32L_I2C_OAR1(n) REG16(stm32l_i2c_reg(n, 0x08))
#define STM32L_I2C_OAR2(n) REG16(stm32l_i2c_reg(n, 0x0C))
#define STM32L_I2C_DR(n) REG16(stm32l_i2c_reg(n, 0x10))
#define STM32L_I2C_SR1(n) REG16(stm32l_i2c_reg(n, 0x14))
#define STM32L_I2C_SR2(n) REG16(stm32l_i2c_reg(n, 0x18))
#define STM32L_I2C_CCR(n) REG16(stm32l_i2c_reg(n, 0x1C))
#define STM32L_I2C_TRISE(n) REG16(stm32l_i2c_reg(n, 0x20))
/* --- Power / Reset / Clocks --- */
#define STM32L_PWR_BASE 0x40007000
#define STM32L_PWR_CR REG32(STM32L_PWR_BASE + 0x00)
#define STM32L_PWR_CSR REG32(STM32L_PWR_BASE + 0x04)
#define STM32L_RCC_BASE 0x40023800
#define STM32L_RCC_CR REG32(STM32L_RCC_BASE + 0x00)
#define STM32L_RCC_ICSR REG32(STM32L_RCC_BASE + 0x04)
#define STM32L_RCC_CFGR REG32(STM32L_RCC_BASE + 0x08)
#define STM32L_RCC_CIR REG32(STM32L_RCC_BASE + 0x0C)
#define STM32L_RCC_AHBRSTR REG32(STM32L_RCC_BASE + 0x10)
#define STM32L_RCC_APB2RSTR REG32(STM32L_RCC_BASE + 0x14)
#define STM32L_RCC_APB1RSTR REG32(STM32L_RCC_BASE + 0x18)
#define STM32L_RCC_AHBENR REG32(STM32L_RCC_BASE + 0x1C)
#define STM32L_RCC_APB2ENR REG32(STM32L_RCC_BASE + 0x20)
#define STM32L_RCC_APB1ENR REG32(STM32L_RCC_BASE + 0x24)
#define STM32L_RCC_AHBLPENR REG32(STM32L_RCC_BASE + 0x28)
#define STM32L_RCC_APB2LPENR REG32(STM32L_RCC_BASE + 0x2C)
#define STM32L_RCC_APB1LPENR REG32(STM32L_RCC_BASE + 0x30)
#define STM32L_RCC_CSR REG32(STM32L_RCC_BASE + 0x34)
#define STM32L_SYSCFG_BASE 0x40010000
#define STM32L_SYSCFG_MEMRMP REG32(STM32L_SYSCFG_BASE + 0x00)
#define STM32L_SYSCFG_PMC REG32(STM32L_SYSCFG_BASE + 0x04)
#define STM32L_SYSCFG_EXTICR(n) REG32(STM32L_SYSCFG_BASE + 8 + 4 * (n))
/* --- Watchdogs --- */
#define STM32L_WWDG_BASE 0x40002C00
#define STM32L_WWDG_CR REG32(STM32L_WWDG_BASE + 0x00)
#define STM32L_WWDG_CFR REG32(STM32L_WWDG_BASE + 0x04)
#define STM32L_WWDG_SR REG32(STM32L_WWDG_BASE + 0x08)
#define STM32L_IWDG_BASE 0x40003000
#define STM32L_IWDG_KR REG32(STM32L_IWDG_BASE + 0x00)
#define STM32L_IWDG_PR REG32(STM32L_IWDG_BASE + 0x04)
#define STM32L_IWDG_RLR REG32(STM32L_IWDG_BASE + 0x08)
#define STM32L_IWDG_SR REG32(STM32L_IWDG_BASE + 0x0C)
/* --- Real-Time Clock --- */
#define STM32L_RTC_BASE 0x40002800
#define STM32L_RTC_TR REG32(STM32L_RTC_BASE + 0x00)
#define STM32L_RTC_DR REG32(STM32L_RTC_BASE + 0x04)
#define STM32L_RTC_CR REG32(STM32L_RTC_BASE + 0x08)
#define STM32L_RTC_ISR REG32(STM32L_RTC_BASE + 0x0C)
#define STM32L_RTC_PRER REG32(STM32L_RTC_BASE + 0x10)
#define STM32L_RTC_WUTR REG32(STM32L_RTC_BASE + 0x14)
#define STM32L_RTC_CALIBR REG32(STM32L_RTC_BASE + 0x18)
#define STM32L_RTC_ALRMAR REG32(STM32L_RTC_BASE + 0x1C)
#define STM32L_RTC_ALRMBR REG32(STM32L_RTC_BASE + 0x20)
#define STM32L_RTC_WPR REG32(STM32L_RTC_BASE + 0x24)
#define STM32L_RTC_TSTR REG32(STM32L_RTC_BASE + 0x30)
#define STM32L_RTC_TSDR REG32(STM32L_RTC_BASE + 0x34)
#define STM32L_RTC_TAFCR REG32(STM32L_RTC_BASE + 0x40)
#define STM32L_RTC_BACKUP(n) REG32(STM32L_RTC_BASE + 0x50 + 4 * (n))
/* --- SPI --- */
#define STM32L_SPI1_BASE 0x40013000
#define STM32L_SPI2_BASE 0x40003800
#define STM32L_SPI1_PORT 0
#define STM32L_SPI2_PORT 1
/*
* TODO(vpalatin):
* For whatever reason, our toolchain is substandard and generate a
* function every time you are using this inline function.
*
* That's why I have not used inline stuff in the registers definition.
*/
#define stm32l_spi_addr(port, offset) \
((port == 0) ? \
(STM32L_SPI1_BASE + offset) : \
(STM32L_SPI2_BASE + offset))
#define STM32L_SPI_REG16(p, l) REG16(stm32l_spi_addr((p), l))
#define STM32L_SPI_CR1(p) STM32L_SPI_REG16((p), 0x00)
#define STM32L_SPI_CR2(p) STM32L_SPI_REG16((p), 0x04)
#define STM32L_SPI_SR(p) STM32L_SPI_REG16((p), 0x08)
#define STM32L_SPI_DR(p) STM32L_SPI_REG16((p), 0x0c)
#define STM32L_SPI_CRCPR(p) STM32L_SPI_REG16((p), 0x10)
#define STM32L_SPI_RXCRCR(p) STM32L_SPI_REG16((p), 0x14)
#define STM32L_SPI_TXCRCR(p) STM32L_SPI_REG16((p), 0x18)
/* --- Debug --- */
#define STM32L_DBGMCU_BASE 0xE0042000
#define STM32L_DBGMCU_IDCODE REG32(STM32L_DBGMCU_BASE + 0x00)
#define STM32L_DBGMCU_CR REG32(STM32L_DBGMCU_BASE + 0x04)
#define STM32L_DBGMCU_APB1FZ REG32(STM32L_DBGMCU_BASE + 0x08)
#define STM32L_DBGMCU_APB2FZ REG32(STM32L_DBGMCU_BASE + 0x0C)
/* --- Flash --- */
#define STM32L_FLASH_REGS_BASE 0x40023c00
#define STM32L_FLASH_ACR REG32(STM32L_FLASH_REGS_BASE + 0x00)
/* --- External Interrupts --- */
#define STM32L_EXTI_BASE 0x40010400
#define STM32L_EXTI_IMR REG32(STM32L_EXTI_BASE + 0x00)
#define STM32L_EXTI_EMR REG32(STM32L_EXTI_BASE + 0x04)
#define STM32L_EXTI_RTSR REG32(STM32L_EXTI_BASE + 0x08)
#define STM32L_EXTI_FTSR REG32(STM32L_EXTI_BASE + 0x0c)
#define STM32L_EXTI_SWIER REG32(STM32L_EXTI_BASE + 0x10)
#define STM32L_EXTI_PR REG32(STM32L_EXTI_BASE + 0x14)
/* --- MISC --- */
#define STM32L_RI_BASE 0x40007C04
#define STM32L_ADC1_BASE 0x40012400
#define STM32L_ADC_BASE 0x40012700
#define STM32L_COMP_BASE 0x40007C00
#define STM32L_DAC_BASE 0x40007400
#define STM32L_CRC_BASE 0x40023000
#define STM32L_LCD_BASE 0x40002400
#define STM32L_DMA1_BASE 0x40026000
#define STM32L_DMA2_BASE 0x40026400
#endif /* __STM32L_REGISTERS */