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grunt: Add delay to PWR_GOOD

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Add delay of 1ms with stable power before asserting PWR_GOOD.
CDX03 seems to work ok with and without the delay, but since it
is a requirement in the electrical data sheet, better add it.

Also removed an unnecessary header while I was here.

BUG=b:70350333
BRANCH=none
TEST=power CDX03 on and off

Change-Id: I9f2f94bfb907ac9e88f350e72286061a97ebfe3d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/816063
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This commit is contained in:
Edward Hill
2017-12-07 16:05:39 -07:00
committed by chrome-bot
parent 359b98c312
commit 716fcb123d
2 changed files with 9 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
power/stoney.c
View File

@@ -21,12 +21,13 @@
#include "util.h"
#include "wireless.h"
#include "registers.h"
#include "stoney.h"
/* Console output macros */
#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
#define IN_SPOK POWER_SIGNAL_MASK(X86_SPOK)
static int forcing_coldreset; /* Forced coldreset in progress? */
static int forcing_shutdown; /* Forced shutdown in progress? */
@@ -108,6 +109,13 @@ static void handle_pass_through(enum power_state state,
if (in_level == out_level)
return;
/*
* SOC requires a delay of 1ms with stable power before
* asserting PWR_GOOD.
*/
if ((pin_in == GPIO_VGATE) && in_level)
msleep(1);
gpio_set_level(pin_out, in_level);
CPRINTS("Pass through %s: %d", gpio_get_name(pin_in), in_level);
@@ -257,10 +265,8 @@ enum power_state power_handle_state(enum power_state state)
{
enum power_state new_state;
/* Process RSMRST_L state changes. */
handle_pass_through(state, GPIO_SPOK, GPIO_PCH_RSMRST_L);
/* Process ALL_SYS_PGOOD state changes. */
handle_pass_through(state, GPIO_VGATE, GPIO_PCH_SYS_PWROK);
new_state = _power_handle_state(state);

17
power/stoney.h
View File

@@ -1,17 +0,0 @@
/* Copyright 2016 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Stoney chipset power control module for Chrome EC */
#ifndef __CROS_EC_STONEY_H
#define __CROS_EC_STONEY_H
#define IN_SPOK POWER_SIGNAL_MASK(X86_SPOK)
#define IN_ALW_PG POWER_SIGNAL_MASK(X86_ALW_PG)
#define IN_SLP_S3 POWER_SIGNAL_MASK(X86_SLP_S3_N)
#define IN_SLP_S5 POWER_SIGNAL_MASK(X86_SLP_S5_N)
#endif /* __CROS_EC_STONEY_H */