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npcx: Apply deep idle bypass for hibernate
Although probability is small, we still have chance to encounter the same symptom which CPU's behavior is abnormal after wake-up from deep idle. Apply the same bypass in task.c but not enable interrupt to solve it. Modified sources: 1. system.c: Apply deep idle bypass for hibernate. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall; test "hibernate"&"hibernate 10" on wheatley. Change-Id: Ib00b9932ac34414d6a177d60668664ab31284a79 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/373300 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
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@@ -255,6 +255,15 @@ void system_mpu_config(void)
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void __keep __attribute__ ((section(".lowpower_ram")))
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__enter_hibernate_in_lpram(void)
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{
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/*
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* TODO (ML): Set stack pointer to upper 512B of Suspend RAM.
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* Our bypass needs stack instructions but FW will turn off main ram
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* later for better power consumption.
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*/
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asm (
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"ldr r0, =0x40001800\n"
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"mov sp, r0\n"
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);
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/* Disable Code RAM first */
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SET_BIT(NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_5), NPCX_PWDWN_CTL5_MRFSH_DIS);
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@@ -262,8 +271,22 @@ __enter_hibernate_in_lpram(void)
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/* Set deep idle mode*/
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NPCX_PMCSR = 0x6;
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/* Enter deep idle, wake-up by GPIOxx or RTC */
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asm("wfi");
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/*
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* TODO (ML): Although the probability is small, it still has chance
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* to meet the same symptom that CPU's behavior is abnormal after
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* wake-up from deep idle.
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* Workaround: Apply the same bypass of idle but don't enable interrupt.
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*/
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asm (
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"push {r0-r5}\n" /* Save needed registers */
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"ldr r0, =0x40001600\n" /* Set r0 to Suspend RAM addr */
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"wfi\n" /* Wait for int to enter idle */
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"ldm r0, {r0-r5}\n" /* Add a delay after WFI */
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"pop {r0-r5}\n" /* Restore regs before enabling ints */
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"isb\n" /* Flush the cpu pipeline */
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);
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/* RTC wake-up */
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if (IS_BIT_SET(NPCX_WTC, NPCX_WTC_PTO))
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