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kevin: Use 32.768KHz input clock for improved RTC accuracy

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BUG=chrome-os-partner:56949
BRANCH=None
TEST=Run stopwatch for 10 minutes, verify 'rtc' time difference matches
stopwatch.

Change-Id: I3aed54b17433f9acfe284e9c8846d4e1e7c1a199
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/381571
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
This commit is contained in:
Shawn Nematbakhsh
2016-09-06 11:31:34 -07:00
committed by chrome-bot
parent 834207c485
commit 764b2e57e7
3 changed files with 11 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
board/kevin/gpio.inc
View File

@@ -87,9 +87,6 @@ GPIO(I2C2_SDA, PIN(9, 1), GPIO_ODR_HIGH)
GPIO(I2C3_SCL, PIN(D, 1), GPIO_ODR_HIGH)
GPIO(I2C3_SDA, PIN(D, 0), GPIO_ODR_HIGH)
/* TODO - configure 32KCLKIN for alternate mode */
GPIO(CLK_32K_IN, PIN(E, 7), GPIO_INPUT)
/* Attached to push-pull interrupt pin of accel, but unused */
GPIO(LID_ACCEL_INT_L, PIN(C, 7), GPIO_INPUT)
@@ -106,7 +103,7 @@ GPIO(EC_BOARD_ID_EN_L, PIN(3, 5), GPIO_OUT_HIGH)
GPIO(USB_DP_HPD, PIN(6, 6), GPIO_OUT_LOW)
GPIO(CHARGER_RESET_L, PIN(0, 1), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
GPIO(CR50_RESET_L, PIN(0, 2), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
GPIO(TPM_ALLOW_RST, PIN(0, 2), GPIO_OUT_HIGH | GPIO_OPEN_DRAIN)
GPIO(EC_BATT_PRES_L, PIN(3, 4), GPIO_INPUT)
GPIO(LID_360_L, PIN(3, 6), GPIO_INPUT | GPIO_SEL_1P8V)
GPIO(BASE_SIXAXIS_INT_L, PIN(4, 0), GPIO_INPUT | GPIO_SEL_1P8V)
@@ -174,3 +171,6 @@ ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
/* Keyboard Rows */
ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, 0)
ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, 0)
/* External 32KHz input clock - GPIOE7 */
ALTERNATE(PIN_MASK(E, 0x80), 1, MODULE_CLOCK, 0)

3
chip/npcx/clock.c
View File

@@ -159,6 +159,9 @@ void clock_init(void)
/* Notify modules of frequency change */
hook_notify(HOOK_FREQ_CHANGE);
/* Configure alt. clock GPIOs (eg. optional 32KHz clock) */
gpio_config_module(MODULE_CLOCK, 1);
}
/**

4
chip/npcx/gpio.c
View File

@@ -232,6 +232,7 @@ BUILD_ASSERT(sizeof(struct gpio_alt_map) == 2);
#define NPCX_ALT(grp, pin) { ALT_GROUP_##grp, NPCX_DEVALT##grp##_##pin, 0 }
#define NPCX_ALT_INV(grp, pin) { ALT_GROUP_##grp, NPCX_DEVALT##grp##_##pin, 1 }
/* TODO: Index this table on GPIO# */
const struct gpio_alt_map gpio_alt_table[] = {
/* I2C Module */
{ NPCX_GPIO(B, 2), NPCX_ALT(2, I2C0_1_SL)}, /* SMB0SDA1 */
@@ -308,6 +309,9 @@ const struct gpio_alt_map gpio_alt_table[] = {
{ NPCX_GPIO(8, 3), NPCX_ALT_INV(9, NO_KSO15_SL)},/* KSO15 */
{ NPCX_GPIO(0, 3), NPCX_ALT_INV(A, NO_KSO16_SL)},/* KSO16 */
{ NPCX_GPIO(B, 1), NPCX_ALT_INV(A, NO_KSO17_SL)},/* KSO17 */
/* Clock module */
{ NPCX_GPIO(7, 5), NPCX_ALT(A, 32K_OUT_SL)}, /* 32KHZ_OUT */
{ NPCX_GPIO(E, 7), NPCX_ALT(A, 32KCLKIN_SL)}, /* 32KCLKIN */
};
struct gpio_lvol_item {