bip: initial add of bip skeleton

BRANCH=none
BUG=b:75972988
TEST=build all

Change-Id: Ibfadaee3b9584a7e2c87f6f607be4cba20f338b7
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/972142
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>

board/bip/board.c

@@ -0,0 +1,123 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Bip board-specific configuration */
+
+#include "common.h"
+#include "ec2i_chip.h"
+#include "gpio.h"
+#include "lid_switch.h"
+#include "power_button.h"
+#include "spi.h"
+#include "switch.h"
+#include "system.h"
+#include "util.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+/******************************************************************************/
+/* Wake up pins */
+/* TODO(b/73811887): Fill out correctly */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
+/******************************************************************************/
+/* SPI devices */
+/* TODO(b/73811887): Fill out correctly (SPI FLASH) */
+const struct spi_device_t spi_devices[] = {
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
+
+/******************************************************************************/
+/* PNPCFG settings */
+/* TODO(b/76022972): Ensure correct and put in common chip code instead */
+const struct ec2i_t pnpcfg_settings[] = {
+	/* Select logical device 06h(keyboard) */
+	{HOST_INDEX_LDN, LDN_KBC_KEYBOARD},
+	/* Set IRQ=01h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x01},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 05h(mouse) */
+	{HOST_INDEX_LDN, LDN_KBC_MOUSE},
+	/* Set IRQ=0Ch for logical device */
+	{HOST_INDEX_IRQNUMX, 0x0C},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 11h(PM1 ACPI) */
+	{HOST_INDEX_LDN, LDN_PMC1},
+	/* Set IRQ=00h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x00},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 12h(PM2) */
+	{HOST_INDEX_LDN, LDN_PMC2},
+	/* I/O Port Base Address 200h/204h */
+	{HOST_INDEX_IOBAD0_MSB, 0x02},
+	{HOST_INDEX_IOBAD0_LSB, 0x00},
+	{HOST_INDEX_IOBAD1_MSB, 0x02},
+	{HOST_INDEX_IOBAD1_LSB, 0x04},
+	/* Set IRQ=00h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x00},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 0Fh(SMFI) */
+	{HOST_INDEX_LDN, LDN_SMFI},
+	/* H2RAM LPC I/O cycle Dxxx */
+	{HOST_INDEX_DSLDC6, 0x00},
+	/* Enable H2RAM LPC I/O cycle */
+	{HOST_INDEX_DSLDC7, 0x01},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+
+	/* Select logical device 17h(PM3) */
+	{HOST_INDEX_LDN, LDN_PMC3},
+	/* I/O Port Base Address 80h */
+	{HOST_INDEX_IOBAD0_MSB, 0x00},
+	{HOST_INDEX_IOBAD0_LSB, 0x80},
+	{HOST_INDEX_IOBAD1_MSB, 0x00},
+	{HOST_INDEX_IOBAD1_LSB, 0x00},
+	/* Set IRQ=00h for logical device */
+	{HOST_INDEX_IRQNUMX, 0x00},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+	/* Select logical device 10h(RTCT) */
+	{HOST_INDEX_LDN, LDN_RTCT},
+	/* P80L Begin Index */
+	{HOST_INDEX_DSLDC4, P80L_P80LB},
+	/* P80L End Index */
+	{HOST_INDEX_DSLDC5, P80L_P80LE},
+	/* P80L Current Index */
+	{HOST_INDEX_DSLDC6, P80L_P80LC},
+#ifdef CONFIG_UART_HOST
+	/* Select logical device 2h(UART2) */
+	{HOST_INDEX_LDN, LDN_UART2},
+	/*
+	 * I/O port base address is 2F8h.
+	 * Host can use LPC I/O port 0x2F8 ~ 0x2FF to access UART2.
+	 * See specification 7.24.4 for more detial.
+	 */
+	{HOST_INDEX_IOBAD0_MSB, 0x02},
+	{HOST_INDEX_IOBAD0_LSB, 0xF8},
+	/* IRQ number is 3 */
+	{HOST_INDEX_IRQNUMX, 0x03},
+	/*
+	 * Interrupt Request Type Select
+	 * bit1, 0: IRQ request is buffered and applied to SERIRQ.
+	 *       1: IRQ request is inverted before being applied to SERIRQ.
+	 * bit0, 0: Edge triggered mode.
+	 *       1: Level triggered mode.
+	 */
+	{HOST_INDEX_IRQTP, 0x02},
+	/* Enable logical device */
+	{HOST_INDEX_LDA, 0x01},
+#endif
+};
+BUILD_ASSERT(ARRAY_SIZE(pnpcfg_settings) == EC2I_SETTING_COUNT);

board/bip/board.h

@@ -0,0 +1,36 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Bip board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Optional features */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+
+#define CONFIG_POWER_BUTTON
+#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_LOW_POWER_IDLE
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* TODO(b/75972988): Fill out correctly */
+enum adc_channel {
+	ADC_CH_COUNT
+};
+
+/* TODO(b/75972988): Fill out correctly */
+enum pwm_channel {
+	PWM_CH_COUNT
+};
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */

board/bip/build.mk

@@ -0,0 +1,12 @@
+# -*- makefile -*-
+# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=it83xx
+BASEBOARD:=octopus
+
+board-y=board.o

board/bip/ec.tasklist

@@ -0,0 +1,27 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ *
+ * For USB PD tasks, IDs must be in consecutive order and correspond to
+ * the port which they are for. See TASK_ID_TO_PD_PORT() macro.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)

board/bip/gpio.inc

@@ -0,0 +1,29 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+/* Wake Source interrupts */
+GPIO_INT(LID_OPEN,	 PIN(E, 2), GPIO_INT_BOTH |
+				    GPIO_HIB_WAKE_HIGH, lid_interrupt)
+GPIO_INT(WP_L,		 PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)		/* EC_WP_ODL */
+GPIO_INT(POWER_BUTTON_L, PIN(E, 4), GPIO_INT_BOTH, power_button_interrupt)	/* MECH_PWR_BTN_ODL */
+
+/*
+ * TODO(b/76023457): Move below 4 signals to virtual wires over eSPI
+ */
+GPIO(PCH_PLTRST_L,	 PIN(E, 3), GPIO_INPUT)		/* PLT_RST_L: Platform Reset from SoC */
+GPIO(PCH_RCIN_L,	 PIN(B, 6), GPIO_ODR_HIGH)	/* SYS_RST_ODL */
+GPIO(PCH_SMI_L,		 PIN(D, 4), GPIO_OUT_LOW)	/* EC_SMI_R_ODL */
+GPIO(PCH_SCI_L,		 PIN(D, 3), GPIO_OUT_LOW)	/* EC_SCI_R_ODL */
+
+GPIO(ENTERING_RW,	 PIN(C, 5), GPIO_OUT_LOW)	/* EC_ENTERING_RW */
+GPIO(PCH_WAKE_L,	 PIN(D, 1), GPIO_ODR_HIGH)	/* EC_PCH_WAKE_ODL */
+
+/* TODO(b/76022415): Determine if low power mode really needs interrupt here */
+UNIMPLEMENTED(UART1_RX)

util/flash_ec

@@ -46,6 +46,7 @@ die() {
 
 
 BOARDS_IT83XX=(
+	bip
 	it83xx_evb
 	reef_it8320
 )