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stm32l: implement reset cause and scratchpad

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Allow to get proper reset reason.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BUG=None
TEST=On the discovery board, try the reset button, the "reboot" command
and a blocking wait, and see the proper reset reason displayed.
Initialize the scratchpad register with "setscratchpad" command and
check we can read it back after reboot.

Change-Id: I1fe1eec4987f7c9816454de4fd3b4addda4ad05a
This commit is contained in:
Vincent Palatin
2012-02-02 19:08:49 +00:00
parent f771cca719
commit 77b154dd71
1 changed files with 51 additions and 3 deletions
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54
chip/stm32l/system.c
View File

@@ -6,12 +6,35 @@
/* System module for Chrome EC : hardware specific implementation */
#include "cpu.h"
#include "registers.h"
#include "system.h"
static void check_reset_cause(void)
{
system_set_reset_cause(SYSTEM_RESET_UNKNOWN);
enum system_image_copy_t copy = system_get_image_copy();
enum system_reset_cause_t reset_cause = SYSTEM_RESET_UNKNOWN;
uint32_t raw_cause = STM32L_RCC_CSR;
if (copy == SYSTEM_IMAGE_RW_A || copy == SYSTEM_IMAGE_RW_B) {
/* If we're in image A or B, the only way we can get there is
* via a warm reset. */
reset_cause = SYSTEM_RESET_SOFT_WARM;
} else if (raw_cause & 0x60000000) {
/* IWDG pr WWDG */
reset_cause = SYSTEM_RESET_WATCHDOG;
} else if (raw_cause & 0x10000000) {
reset_cause = SYSTEM_RESET_SOFT_COLD;
} else if (raw_cause & 0x08000000) {
reset_cause = SYSTEM_RESET_POWER_ON;
} else if (raw_cause & 0x04000000) {
reset_cause = SYSTEM_RESET_RESET_PIN;
} else if (raw_cause & 0xFE000000) {
reset_cause = SYSTEM_RESET_OTHER;
} else {
reset_cause = SYSTEM_RESET_UNKNOWN;
}
system_set_reset_cause(reset_cause);
}
@@ -19,12 +42,30 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
{
/* we are going to hibernate ... */
while (1)
;
/* NOT IMPLEMENTED */;
}
int system_pre_init(void)
{
/* enable clock on Power module */
STM32L_RCC_APB1ENR |= 1 << 28;
/* Enable access to RCC CSR register and RTC backup registers */
STM32L_PWR_CR |= 1 << 8;
/* switch on LSI */
STM32L_RCC_CSR |= 1 << 0;
/* Wait for LSI to be ready */
while (!(STM32L_RCC_CSR & (1 << 1)))
;
/* re-configure RTC if needed */
if ((STM32L_RCC_CSR & 0x00C30000) != 0x00420000) {
/* the RTC settings are bad, we need to reset it */
STM32L_RCC_CSR |= 0x00800000;
/* Enable RTC and use LSI as clock source */
STM32L_RCC_CSR = (STM32L_RCC_CSR & ~0x00C30000) | 0x00420000;
}
check_reset_cause();
return EC_SUCCESS;
@@ -33,6 +74,11 @@ int system_pre_init(void)
int system_init(void)
{
/* Clear the hardware reset cause by setting the RMVF bit,
* now that we've committed to running this image.
*/
STM32L_RCC_CSR |= 1 << 24;
return EC_SUCCESS;
}
@@ -55,11 +101,13 @@ int system_reset(int is_cold)
int system_set_scratchpad(uint32_t value)
{
STM32L_RTC_BACKUP(0) = value;
return EC_SUCCESS;
}
uint32_t system_get_scratchpad(void)
{
return 0xdeadbeef;
return STM32L_RTC_BACKUP(0);
}