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stm32: add STM32F03x configuration

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Add STM32F03x as part of the STM32F0 family.
STM32F031 will be used for devices requiring low-end parts.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=none
TEST=along with the following CLs, run on STM32F051 Discovery with
limited RAM and Flash to mimic STM32F031.

Change-Id: Ie95303eaf00ce53fe7c8d2ac84c19a983aadbf0d
Reviewed-on: https://chromium-review.googlesource.com/189404
Reviewed-by: Vic Yang <victoryang@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Vincent Palatin
2014-03-07 14:44:41 -08:00
committed by chrome-internal-fetch
parent 60e47a730f
commit 7a7c92e15e
3 changed files with 47 additions and 0 deletions
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42
chip/stm32/config-stm32f03x.h Normal file
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@@ -0,0 +1,42 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Memory mapping */
#define CONFIG_FLASH_BASE 0x08000000
#define CONFIG_FLASH_PHYSICAL_SIZE 0x00008000
#define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE
#define CONFIG_FLASH_BANK_SIZE 0x1000
#define CONFIG_FLASH_ERASE_SIZE 0x0400 /* erase bank size */
#define CONFIG_FLASH_WRITE_SIZE 0x0002 /* minimum write size */
/* No page mode on STM32F, so no benefit to larger write sizes */
#define CONFIG_FLASH_WRITE_IDEAL_SIZE 0x0002
#define CONFIG_RAM_BASE 0x20000000
#define CONFIG_RAM_SIZE 0x00001000
/* Size of one firmware image in flash */
#define CONFIG_FW_IMAGE_SIZE (16 * 1024)
#define CONFIG_FW_RO_OFF 0
#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF
#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_IMAGE_SIZE
/*
* Put pstate after RO to give RW more space and make RO write protect region
* contiguous.
*/
#define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE
#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
/* Number of IRQ vectors on the NVIC */
#define CONFIG_IRQ_COUNT 32
/* Reduced history because of limited RAM */
#undef CONFIG_CONSOLE_HISTORY
#define CONFIG_CONSOLE_HISTORY 3

3
chip/stm32/config_chip.h
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@@ -31,6 +31,9 @@
#elif defined(CHIP_VARIANT_STM32F07X)
/* STM32F07xx */
#include "config-stm32f07x.h"
#elif defined(CHIP_VARIANT_STM32F03X)
/* STM32F03x */
#include "config-stm32f03x.h"
#else
#error "Unsupported chip variant"
#endif

2
util/stm32mon.c
View File

@@ -57,6 +57,8 @@ struct stm32_def {
{0x427, "STM32L15xxC", 0x08000000, 0x40000, 256},
{0x420, "STM32F100xx", 0x08000000, 0x20000, 1024},
{0x410, "STM32F102R8", 0x08000000, 0x10000, 1024},
{0x440, "STM32F05x", 0x08000000, 0x10000, 1024},
{0x444, "STM32F03x", 0x08000000, 0x10000, 1024},
{0x448, "STM32F07xB", 0x08000000, 0x20000, 1024},
{ 0 }
};