scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-01 21:02:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

Keyborg: Switch to HSE

Browse Source 
We have a 16MHz oscillator input, so let's use it to save HSI power.

BUG=None
TEST=Build and boot
BRANCH=None

Change-Id: Ia2d97cfc8b97b7f8661112ebbd84952e41b955f2
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/200650
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Vic Yang
2014-05-20 14:21:58 -07:00
committed by chrome-internal-fetch
parent 724cfbc6c4
commit 7dd3ee4db3
2 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
board/keyborg/hardware.c
View File

@@ -14,17 +14,17 @@
static void clock_init(void)
{
/* Ensure that HSI is ON */
if (!(STM32_RCC_CR & (1 << 1))) {
/* Enable HSI */
STM32_RCC_CR |= 1 << 0;
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR & (1 << 1)))
/* Turn on HSE */
if (!(STM32_RCC_CR & (1 << 17))) {
/* Enable HSE */
STM32_RCC_CR |= (1 << 18) | (1 << 16);
/* Wait for HSE to be ready */
while (!(STM32_RCC_CR & (1 << 17)))
;
}
/* PLLSRC = HSI/2, PLLMUL = x12 (x HSI/2) = 48MHz */
STM32_RCC_CFGR = 0x00684000;
/* PLLSRC = HSE/2 = 8MHz, PLLMUL = x6 = 48MHz */
STM32_RCC_CFGR = 0x00534000;
/* Enable PLL */
STM32_RCC_CR |= 1 << 24;
/* Wait for PLL to be ready */
@@ -32,7 +32,7 @@ static void clock_init(void)
;
/* switch SYSCLK to PLL */
STM32_RCC_CFGR = 0x00684002;
STM32_RCC_CFGR = 0x00534002;
/* wait until the PLL is the clock source */
while ((STM32_RCC_CFGR & 0xc) != 0x8)
;

2
chip/stm32/clock-stm32f.c
View File

@@ -130,7 +130,7 @@ DECLARE_IRQ(STM32_IRQ_RTC_ALARM, __rtc_alarm_irq, 1);
#define RCC_CFGR 0x00680000
#elif defined(BOARD_KEYBORG)
#define DESIRED_CPU_CLOCK 48000000
#define RCC_CFGR 0x00684000
#define RCC_CFGR 0x00534000
#else
#error "Need board-specific clock settings"
#endif