mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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stm32: USB Power Delivery physical layer
Implementation of the physical layer for USB Power Delivery communication using the STM32 chip. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I2a4adeef572b97a284bf52ab9d14d23246c56d18 Reviewed-on: https://chromium-review.googlesource.com/189867 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Vincent Palatin
committed by
chrome-internal-fetch
chrome-internal-fetch
parent
d4c939e9ee
commit
828c1a384a
@@ -37,3 +37,4 @@ chip-$(HAS_TASK_POWERLED)+=power_led.o
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chip-$(CONFIG_FLASH)+=flash-$(FLASH_FAMILY).o
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chip-$(CONFIG_ADC)+=adc-$(CHIP_FAMILY).o
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chip-$(CONFIG_PWM)+=pwm.o
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chip-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_phy.o
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@@ -670,6 +670,7 @@ typedef volatile struct stm32_spi_regs stm32_spi_regs_t;
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#define STM32_SPI_CR1_MSTR (1 << 2)
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#define STM32_SPI_CR2_RXDMAEN (1 << 0)
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#define STM32_SPI_CR2_TXDMAEN (1 << 1)
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#define STM32_SPI_CR2_DATASIZE(n) (((n) - 1) << 8)
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/* --- Debug --- */
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495
chip/stm32/usb_pd_phy.c
Normal file
495
chip/stm32/usb_pd_phy.c
Normal file
@@ -0,0 +1,495 @@
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "adc.h"
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#include "clock.h"
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#include "common.h"
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#include "console.h"
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#include "dma.h"
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#include "gpio.h"
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#include "hwtimer.h"
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#include "hooks.h"
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#include "registers.h"
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#include "task.h"
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#include "timer.h"
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#include "util.h"
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#include "usb_pd.h"
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#include "usb_pd_config.h"
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#ifdef CONFIG_COMMON_RUNTIME
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#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
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#else
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#define CPRINTF(format, args...)
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#endif
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#define PD_DATARATE 300000 /* Hz */
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/*
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* Maximum size of a Power Delivery packet (in bits on the wire) :
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* 16-bit header + 0..7 32-bit data objects (+ 4b5b encoding)
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* 64-bit preamble + SOP (4x 5b) + message in 4b5b + 32-bit CRC + EOP (1x 5b)
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* = 64 + 4*5 + 16 * 5/4 + 7 * 32 * 5/4 + 32 * 5/4 + 5
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*/
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#define PD_BIT_LEN 429
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#define PD_MAX_RAW_SIZE (PD_BIT_LEN*2)
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/* maximum number of consecutive similar bits with Biphase Mark Coding */
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#define MAX_BITS 2
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/* alternating bit sequence used for packet preamble : 00 10 11 01 00 .. */
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#define PD_PREAMBLE 0xB4B4B4B4 /* starts with 0, ends with 1 */
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#define TX_CLOCK_DIV ((clock_get_freq() / (2*PD_DATARATE)))
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/* threshold for 1 300-khz period */
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#define PERIOD 4
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#define NB_PERIOD(from, to) ((((to) - (from) + (PERIOD/2)) & 0xFF) / PERIOD)
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#define PERIOD_THRESHOLD ((PERIOD + 2*PERIOD) / 2)
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/* Timers used for TX and RX clocking */
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#define TIM_TX TIM_CLOCK_PD_TX
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#define TIM_RX TIM_CLOCK_PD_RX
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#include "crc.h"
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/* samples for the PD messages */
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static uint32_t raw_samples[DIV_ROUND_UP(PD_MAX_RAW_SIZE, sizeof(uint32_t))];
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/* state of the bit decoder */
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static int d_toggle;
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static int d_lastlen;
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static uint32_t d_last;
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void *pd_init_dequeue(void)
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{
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/* preamble ends with 1 */
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d_toggle = 0;
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d_last = 0;
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d_lastlen = 0;
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return raw_samples;
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}
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static int wait_bits(int nb)
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{
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int avail;
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stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX);
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avail = dma_bytes_done(rx, PD_MAX_RAW_SIZE);
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if (avail < nb) { /* no received yet ... */
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timestamp_t deadline = get_time();
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deadline.val += 4 * MAX_BITS * (nb - avail);
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while ((dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb)
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&& get_time().val < deadline.val)
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; /* optimized for latency, not CPU usage ... */
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if (dma_bytes_done(rx, PD_MAX_RAW_SIZE) < nb) {
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CPRINTF("TMOUT RX %d/%d\n",
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dma_bytes_done(rx, PD_MAX_RAW_SIZE), nb);
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return -1;
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}
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}
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return nb;
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}
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int pd_dequeue_bits(void *ctxt, int off, int len, uint32_t *val)
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{
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int w;
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uint8_t cnt = 0xff;
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uint8_t *samples = ctxt;
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while ((d_lastlen < len) && (off < PD_MAX_RAW_SIZE - 1)) {
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w = wait_bits(off + 2);
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if (w < 0)
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goto stream_err;
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cnt = samples[off] - samples[off-1];
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if (!cnt || (cnt > 3*PERIOD))
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goto stream_err;
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off++;
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if (cnt <= PERIOD_THRESHOLD) {
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/*
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w = wait_bits(off + 1);
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if (w < 0)
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goto stream_err;
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*/
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cnt = samples[off] - samples[off-1];
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if (cnt > PERIOD_THRESHOLD)
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goto stream_err;
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off++;
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}
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/* enqueue the bit of the last period */
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d_last = (d_last >> 1)
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| (cnt <= PERIOD_THRESHOLD ? 0x80000000 : 0);
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d_lastlen++;
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}
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if (off < PD_MAX_RAW_SIZE) {
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*val = (d_last << (d_lastlen - len)) >> (32 - len);
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d_lastlen -= len;
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return off;
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} else {
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return -1;
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}
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stream_err:
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CPRINTF("Invalid %d @%d\n", cnt, off);
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return -1;
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}
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int pd_find_preamble(void *ctxt)
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{
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int bit;
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uint8_t *vals = ctxt;
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/*
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* Detect preamble
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* Alternate 1-period 1-period & 2-period.
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*/
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uint32_t all = 0;
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stm32_dma_chan_t *rx = dma_get_channel(DMAC_TIM_RX);
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for (bit = 1; bit < PD_MAX_RAW_SIZE - 1; bit++) {
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uint8_t cnt;
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/* wait if the bit is not received yet ... */
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if (PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) {
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while ((PD_MAX_RAW_SIZE - rx->cndtr < bit + 1) &&
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!(STM32_TIM_SR(TIM_RX) & 4))
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;
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if (STM32_TIM_SR(TIM_RX) & 4) {
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CPRINTF("TMOUT RX %d/%d\n",
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PD_MAX_RAW_SIZE - rx->cndtr, bit);
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return -1;
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}
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}
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cnt = vals[bit] - vals[bit-1];
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all = (all >> 1) | (cnt <= PERIOD_THRESHOLD ? 1 << 31 : 0);
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if (all == 0x36db6db6)
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return bit - 1; /* should be SYNC-1 */
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if (all == 0xF33F3F3F)
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return -2; /* got HARD-RESET */
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}
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return -1;
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}
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static int b_toggle;
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int pd_write_preamble(void *ctxt)
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{
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uint32_t *msg = ctxt;
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/* 64-bit x2 preamble */
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msg[0] = PD_PREAMBLE;
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msg[1] = PD_PREAMBLE;
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msg[2] = PD_PREAMBLE;
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msg[3] = PD_PREAMBLE;
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b_toggle = 0x3FF; /* preamble ends with 1 */
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return 2*64;
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}
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int pd_write_sym(void *ctxt, int bit_off, uint32_t val10)
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{
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uint32_t *msg = ctxt;
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int word_idx = bit_off / 32;
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int bit_idx = bit_off % 32;
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uint32_t val = b_toggle ^ val10;
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b_toggle = val & 0x200 ? 0x3FF : 0;
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if (bit_idx <= 22) {
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if (bit_idx == 0)
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msg[word_idx] = 0;
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msg[word_idx] |= val << bit_idx;
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} else {
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msg[word_idx] |= val << bit_idx;
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msg[word_idx+1] = val >> (32 - bit_idx);
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/* side effect: clear the new word when starting it */
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}
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return bit_off + 5*2;
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}
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int pd_write_last_edge(void *ctxt, int bit_off)
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{
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uint32_t *msg = ctxt;
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int word_idx = bit_off / 32;
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int bit_idx = bit_off % 32;
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if (bit_idx == 0)
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msg[word_idx] = 0;
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if (!b_toggle /* last bit was 0 */) {
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/* transition to 1, then 0 */
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msg[word_idx] |= 1 << bit_idx;
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}
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/* ensure that the trailer is 0 */
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msg[word_idx+1] = 0;
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return bit_off + 2;
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}
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#ifdef CONFIG_COMMON_RUNTIME
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void pd_dump_packet(void *ctxt, const char *msg)
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{
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uint8_t *vals = ctxt;
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int bit;
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CPRINTF("ERR %s:\n000:- ", msg);
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/* Packet debug output */
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for (bit = 1; bit < PD_MAX_RAW_SIZE; bit++) {
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int cnt = NB_PERIOD(vals[bit-1], vals[bit]);
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if ((bit & 31) == 0)
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CPRINTF("\n%03d:", bit);
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CPRINTF("%1d ", cnt);
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}
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CPRINTF("><\n");
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cflush();
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for (bit = 0; bit < PD_MAX_RAW_SIZE; bit++) {
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if ((bit & 31) == 0)
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CPRINTF("\n%03d:", bit);
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CPRINTF("%02x ", vals[bit]);
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}
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CPRINTF("||\n");
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cflush();
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}
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#endif /* CONFIG_COMMON_RUNTIME */
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/* --- SPI TX operation --- */
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static const struct dma_option dma_tx_option = {
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DMAC_SPI_TX, (void *)&SPI_REGS->dr,
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STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_8_BIT
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};
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void pd_start_tx(void *ctxt, int bit_len)
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{
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stm32_dma_chan_t *tx = dma_get_channel(DMAC_SPI_TX);
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/* update DMA configuration */
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dma_prepare_tx(&dma_tx_option, DIV_ROUND_UP(bit_len, 8), ctxt);
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/* Flush data in write buffer so that DMA can get the lastest data */
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asm volatile("dmb;");
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/* Kick off the DMA to send the data */
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dma_go(tx);
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/* disable RX detection interrupt */
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pd_rx_disable_monitoring();
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/*
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* Drive the CC line from the TX block :
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* - set the low level reference.
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* - put SPI function on TX pin.
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*/
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pd_tx_enable();
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/* Start counting at 300Khz*/
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STM32_TIM_CR1(TIM_TX) |= 1;
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}
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void pd_tx_done(void)
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{
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stm32_spi_regs_t *spi = SPI_REGS;
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dma_wait(DMAC_SPI_TX);
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/* wait for real end of transmission */
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#ifdef CHIP_FAMILY_STM32F0
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while ((spi->sr & (3<<11)))
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; /* wait for TX FIFO empty */
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#else
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while (!(spi->sr & (1<<1)))
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; /* wait for TXE == 1 */
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#endif
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while (spi->sr & (1<<7))
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; /* wait for BSY == 0 */
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/* ensure that we are not pushing out junk */
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*(uint8_t *)&spi->dr = 0;
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/* Stop counting */
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STM32_TIM_CR1(TIM_TX) &= ~1;
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/* clear tranfer flag */
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dma_clear_isr(DMAC_SPI_TX);
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/* put TX pins and reference in Hi-Z */
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pd_tx_disable();
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}
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/* --- RX operation using comparator linked to timer --- */
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static const struct dma_option dma_tim_option = {
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DMAC_TIM_RX, (void *)&STM32_TIM_CCRx(TIM_RX, TIM_CCR_IDX),
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STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT,
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};
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void pd_rx_start(void)
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{
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/* start sampling the edges on the CC line using the RX timer */
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dma_start_rx(&dma_tim_option, PD_MAX_RAW_SIZE, raw_samples);
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/* enable TIM2 DMA requests */
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STM32_TIM_EGR(TIM_RX) = 0x0001; /* reset counter / reload PSC */;
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STM32_TIM_SR(TIM_RX) = 0; /* clear overflows */
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STM32_TIM_CR1(TIM_RX) |= 1;
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}
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void pd_rx_complete(void)
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{
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/* stop stampling TIM2 */
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STM32_TIM_CR1(TIM_RX) &= ~1;
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/* stop DMA */
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dma_disable(DMAC_TIM_RX);
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}
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void pd_rx_enable_monitoring(void)
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{
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/* clear comparator external interrupt */
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STM32_EXTI_PR = 1 << EXTI_COMP;
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/* clean up older comparator event */
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task_clear_pending_irq(IRQ_COMP);
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/* re-enable comparator interrupt to detect packets */
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task_enable_irq(IRQ_COMP);
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}
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void pd_rx_disable_monitoring(void)
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{
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/* stop monitoring RX during sampling */
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task_disable_irq(IRQ_COMP);
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/* clear comparator external interrupt */
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STM32_EXTI_PR = 1 << EXTI_COMP;
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}
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/* detect an edge on the PD RX pin */
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void pd_rx_handler(void)
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{
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/* start sampling */
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pd_rx_start();
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/* ignore the comparator IRQ until we are done with current message */
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pd_rx_disable_monitoring();
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/* trigger the analysis in the task */
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pd_rx_event();
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}
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DECLARE_IRQ(STM32_IRQ_COMP, pd_rx_handler, 1);
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/* --- Startup initialization --- */
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void *pd_hw_init(void)
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{
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stm32_spi_regs_t *spi = SPI_REGS;
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/* set 40 MHz pin speed on communication pins */
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pd_set_pins_speed();
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/* --- SPI init --- */
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/* Enable clocks to SPI module */
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spi_enable_clock();
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/* Initialize TX pins and put them in Hi-Z */
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pd_tx_init();
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/* Enable Tx DMA for our first transaction */
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spi->cr2 = STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_DATASIZE(8);
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/* Enable the salve SPI: LSB first, force NSS, TX only */
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spi->cr1 = STM32_SPI_CR1_SPE | STM32_SPI_CR1_LSBFIRST
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| STM32_SPI_CR1_SSM | STM32_SPI_CR1_BIDIMODE
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| STM32_SPI_CR1_BIDIOE;
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/* configure TX DMA */
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dma_prepare_tx(&dma_tx_option, PD_MAX_RAW_SIZE, raw_samples);
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/* --- set the TX timer with updates at 600KHz (BMC frequency) --- */
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__hw_timer_enable_clock(TIM_TX, 1);
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/* Timer configuration */
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STM32_TIM_CR1(TIM_TX) = 0x0000;
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STM32_TIM_CR2(TIM_TX) = 0x0000;
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STM32_TIM_DIER(TIM_TX) = 0x0000;
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/* Auto-reload value : 600000 Khz overflow */
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STM32_TIM_ARR(TIM_TX) = TX_CLOCK_DIV;
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/* 50% duty cycle on the output */
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STM32_TIM_CCR1(TIM_TX) = STM32_TIM_ARR(TIM_TX) / 2;
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/* Timer CH1 output configuration */
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STM32_TIM_CCMR1(TIM_TX) = (6 << 4) | (1 << 3);
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STM32_TIM_CCER(TIM_TX) = 1;
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STM32_TIM_BDTR(TIM_TX) = 0x8000;
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/* set prescaler to /1 */
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STM32_TIM_PSC(TIM_TX) = 0;
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/* Reload the pre-scaler and reset the counter */
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STM32_TIM_EGR(TIM_TX) = 0x0001;
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/* --- set counter for RX timing : 2.4Mhz rate, free-running --- */
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__hw_timer_enable_clock(TIM_RX, 1);
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/* Timer configuration */
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STM32_TIM_CR1(TIM_RX) = 0x0000;
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STM32_TIM_CR2(TIM_RX) = 0x0000;
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STM32_TIM_DIER(TIM_RX) = 0x0000;
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/* Auto-reload value : 16-bit free running counter */
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STM32_TIM_ARR(TIM_RX) = 0xFFFF;
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/* Timeout for message receive : 2.7ms */
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STM32_TIM_CCR2(TIM_RX) = clock_get_freq() / (RX_CLOCK_DIV + 1)
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* 27 / 10000 /* 2.7 ms */;
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/* Timer ICx input configuration */
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#if TIM_CCR_IDX == 1
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STM32_TIM_CCMR1(TIM_RX) = TIM_CCR_CS << 0;
|
||||
#elif TIM_CCR_IDX == 4
|
||||
STM32_TIM_CCMR2(TIM_RX) = TIM_CCR_CS << 8;
|
||||
#else
|
||||
#error Unsupported RX timer capture input
|
||||
#endif
|
||||
STM32_TIM_CCER(TIM_RX) = 0xB << ((TIM_CCR_IDX - 1) * 4);
|
||||
/* configure DMA request on CCRx update */
|
||||
STM32_TIM_DIER(TIM_RX) |= 1 << (8 + TIM_CCR_IDX); /* CCxDE */;
|
||||
/* set prescaler to /26 (F=1.2Mhz, T=0.8us) */
|
||||
STM32_TIM_PSC(TIM_RX) = RX_CLOCK_DIV;
|
||||
/* Reload the pre-scaler and reset the counter */
|
||||
STM32_TIM_EGR(TIM_RX) = 0x0001 | (1 << TIM_CCR_IDX) /* clear CCRx */;
|
||||
/* clear update event from reloading */
|
||||
STM32_TIM_SR(TIM_RX) = 0;
|
||||
|
||||
/* --- DAC configuration for comparator at 850mV --- */
|
||||
#ifdef CONFIG_PD_USE_DAC_AS_REF
|
||||
/* Enable DAC interface clock. */
|
||||
STM32_RCC_APB1ENR |= (1 << 29);
|
||||
/* set voltage Vout=0.850V (Vref = 3.0V) */
|
||||
STM32_DAC_DHR12RD = 850 * 4096 / 3000;
|
||||
/* Start DAC channel 1 */
|
||||
STM32_DAC_CR = STM32_DAC_CR_EN1;
|
||||
#endif
|
||||
|
||||
/* --- COMP2 as comparator for RX vs Vmid = 850mV --- */
|
||||
#ifdef CONFIG_USB_PD_INTERNAL_COMP
|
||||
#if defined(CHIP_FAMILY_STM32F0)
|
||||
/* 40 MHz pin speed on PA0 and PA4 */
|
||||
STM32_GPIO_OSPEEDR(GPIO_A) |= 0x303;
|
||||
/* turn on COMP/SYSCFG */
|
||||
STM32_RCC_APB2ENR |= 1 << 0;
|
||||
/* currently in hi-speed mode : TODO revisit later, INM = PA0(INM6) */
|
||||
STM32_COMP_CSR = STM32_COMP_CMP1EN | STM32_COMP_CMP1MODE_LSPEED |
|
||||
STM32_COMP_CMP1INSEL_INM6 |
|
||||
STM32_COMP_CMP1OUTSEL_TIM1_IC1 |
|
||||
STM32_COMP_CMP1HYST_HI;
|
||||
#elif defined(CHIP_FAMILY_STM32L)
|
||||
/* 40 MHz pin speed on PB4 */
|
||||
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x300;
|
||||
|
||||
STM32_RCC_APB1ENR |= 1 << 31; /* turn on COMP */
|
||||
|
||||
STM32_COMP_CSR = STM32_COMP_OUTSEL_TIM2_IC4 | STM32_COMP_INSEL_DAC_OUT1
|
||||
| STM32_COMP_SPEED_FAST;
|
||||
/* route PB4 to COMP input2 through GR6_1 bit 4 (or PB5->GR6_2 bit 5) */
|
||||
STM32_RI_ASCR2 |= 1 << 4;
|
||||
#else
|
||||
#error Unsupported chip family
|
||||
#endif
|
||||
#endif /* CONFIG_USB_PD_INTERNAL_COMP */
|
||||
/* DBG */usleep(250000);
|
||||
/* comparator interrupt setup */
|
||||
EXTI_XTSR |= 1 << EXTI_COMP;
|
||||
STM32_EXTI_IMR |= 1 << EXTI_COMP;
|
||||
task_enable_irq(IRQ_COMP);
|
||||
|
||||
CPRINTF("USB PD initialized\n");
|
||||
return raw_samples;
|
||||
}
|
||||
|
||||
void pd_set_clock(int freq)
|
||||
{
|
||||
STM32_TIM_ARR(TIM_TX) = clock_get_freq() / (2*freq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_PD_DUAL_ROLE
|
||||
void pd_set_host_mode(int enable)
|
||||
{
|
||||
gpio_set_level(GPIO_CC_HOST, enable);
|
||||
}
|
||||
#endif /* CONFIG_USB_PD_DUAL_ROLE */
|
||||
Reference in New Issue
Block a user