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stm32/usb: Add useful register macros instead of hardcoding values

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Hopefully makes the code a little easier to understand, and will
be useful for future features.

BRANCH=none
BUG=chrome-os-partner:62325
TEST=build and flash hammer

Change-Id: I2b562740794c165da4e6611be371926e737f3887
Reviewed-on: https://chromium-review.googlesource.com/446238
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Nicolas Boichat
2017-02-22 17:01:18 +08:00
committed by chrome-bot
parent 6d9dd9502e
commit 8290f06283
2 changed files with 39 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
chip/stm32/registers.h
View File

@@ -2125,7 +2125,37 @@ typedef volatile struct stm32_dma_regs stm32_dma_regs_t;
#define STM32_USB_EP(n) REG16(STM32_USB_FS_BASE + (n) * 4)
#define STM32_USB_CNTR REG16(STM32_USB_FS_BASE + 0x40)
#define STM32_USB_CNTR_FRES (1 << 0)
#define STM32_USB_CNTR_PDWN (1 << 1)
#define STM32_USB_CNTR_LP_MODE (1 << 2)
#define STM32_USB_CNTR_FSUSP (1 << 3)
#define STM32_USB_CNTR_RESUME (1 << 4)
#define STM32_USB_CNTR_L1RESUME (1 << 5)
#define STM32_USB_CNTR_L1REQM (1 << 7)
#define STM32_USB_CNTR_ESOFM (1 << 8)
#define STM32_USB_CNTR_SOFM (1 << 9)
#define STM32_USB_CNTR_RESETM (1 << 10)
#define STM32_USB_CNTR_SUSPM (1 << 11)
#define STM32_USB_CNTR_WKUPM (1 << 12)
#define STM32_USB_CNTR_ERRM (1 << 13)
#define STM32_USB_CNTR_PMAOVRM (1 << 14)
#define STM32_USB_CNTR_CTRM (1 << 15)
#define STM32_USB_ISTR REG16(STM32_USB_FS_BASE + 0x44)
#define STM32_USB_ISTR_EP_ID_MASK (0x000f)
#define STM32_USB_ISTR_DIR (1 << 4)
#define STM32_USB_ISTR_L1REQ (1 << 7)
#define STM32_USB_ISTR_ESOF (1 << 8)
#define STM32_USB_ISTR_SOF (1 << 9)
#define STM32_USB_ISTR_RESET (1 << 10)
#define STM32_USB_ISTR_SUSP (1 << 11)
#define STM32_USB_ISTR_WKUP (1 << 12)
#define STM32_USB_ISTR_ERR (1 << 13)
#define STM32_USB_ISTR_PMAOVR (1 << 14)
#define STM32_USB_ISTR_CTR (1 << 15)
#define STM32_USB_FNR REG16(STM32_USB_FS_BASE + 0x48)
#define STM32_USB_DADDR REG16(STM32_USB_FS_BASE + 0x4C)
#define STM32_USB_BTABLE REG16(STM32_USB_FS_BASE + 0x50)

15
chip/stm32/usb.c
View File

@@ -296,13 +296,13 @@ void usb_interrupt(void)
{
uint16_t status = STM32_USB_ISTR;
if ((status & (1 << 10)))
if (status & STM32_USB_ISTR_RESET)
usb_reset();
if (status & (1 << 15)) {
int ep = status & 0x000f;
if (status & STM32_USB_ISTR_CTR) {
int ep = status & STM32_USB_ISTR_EP_ID_MASK;
if (ep < USB_EP_COUNT) {
if (status & 0x0010)
if (status & STM32_USB_ISTR_DIR)
usb_ep_rx[ep]();
else
usb_ep_tx[ep]();
@@ -330,7 +330,7 @@ void usb_init(void)
/* power on sequence */
/* keep FRES (USB reset) and remove PDWN (power down) */
STM32_USB_CNTR = 0x01;
STM32_USB_CNTR = STM32_USB_CNTR_FRES;
udelay(1); /* startup time */
/* reset FRES and keep interrupts masked */
STM32_USB_CNTR = 0x00;
@@ -347,7 +347,10 @@ void usb_init(void)
/* Enable interrupt handlers */
task_enable_irq(STM32_IRQ_USB_LP);
/* set interrupts mask : reset/correct transfer/errors */
STM32_USB_CNTR = 0xe400;
STM32_USB_CNTR = STM32_USB_CNTR_CTRM |
STM32_USB_CNTR_PMAOVRM |
STM32_USB_CNTR_ERRM |
STM32_USB_CNTR_RESETM;
#ifdef CONFIG_USB_SERIALNO
usb_load_serial();