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mec1322: Added KBD SERIRQ support

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BUG=chrome-os-partner:24107
TEST=Keyboard keys are printed correctly on Kunimitsu.
BRANCH=none

Change-Id: Ia4ed6c1166fa20dc8623ea8d7147b6f587cbf993
Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/272504
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com>
This commit is contained in:
Kevin K Wong
2015-04-26 23:50:29 -07:00
committed by ChromeOS Commit Bot
parent 3d69e505fc
commit 878c09d64b
1 changed files with 8 additions and 7 deletions
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15
chip/mec1322/lpc.c
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@@ -36,9 +36,9 @@ static int init_done;
static struct ec_lpc_host_args * const lpc_host_args =
(struct ec_lpc_host_args *)mem_mapped;
#ifdef CONFIG_KEYBOARD_IRQ_GPIO
static void keyboard_irq_assert(void)
{
#ifdef CONFIG_KEYBOARD_IRQ_GPIO
/*
* Enforce signal-high for long enough for the signal to be pulled high
* by the external pullup resistor. This ensures the host will see the
@@ -53,15 +53,12 @@ static void keyboard_irq_assert(void)
/* Set signal high, now that we've generated the edge */
gpio_set_level(CONFIG_KEYBOARD_IRQ_GPIO, 1);
}
#else
static void keyboard_irq_assert(void)
{
/*
* TODO(crosbug.com/p/24107): Implement SER_IRQ
* SERIRQ is automatically sent by KBC
*/
}
#endif
}
/**
* Generate SMI pulse to the host chipset via GPIO.
@@ -221,7 +218,11 @@ static void setup_lpc(void)
task_enable_irq(MEC1322_IRQ_8042EM_IBF);
task_enable_irq(MEC1322_IRQ_8042EM_OBF);
/* TODO(crosbug.com/p/24107): Route KIRQ to SER_IRQ1 */
#ifndef CONFIG_KEYBOARD_IRQ_GPIO
/* Set up SERIRQ for keyboard */
MEC1322_8042_KB_CTRL |= (1 << 5);
MEC1322_LPC_SIRQ(1) = 0x01;
#endif
/* Set up EMI module for memory mapped region, base address 0x800 */
MEC1322_LPC_EMI_BAR = 0x0800800f;