mirror of
https://github.com/Telecominfraproject/OpenCellular.git
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pit: Fix watchdog help for STM32L
Clean up timer initialization code to be more general, so that we can
use timer 9 for the LSB on STM32L. Then use timer 4 for the watchdog
helper.
BUG=chrome-os-partner:18781
BRANCH=none
TEST=From EC console:
timerinfo -> current time still counts up properly
waitms 2000 -> prints watchdog info before rebooting
Change-Id: Ib0ba496b0eadb93756dcd1841857546910baf2a9
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59612
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Randall Spangler
committed by
ChromeBot
ChromeBot
parent
c7e60d03aa
commit
8a66ae3182
@@ -49,6 +49,7 @@
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/* Timer selection */
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#define TIM_CLOCK_MSB 3
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#define TIM_CLOCK_LSB 4
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#define TIM_WATCHDOG 1
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/* GPIO signal list */
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enum gpio_signal {
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@@ -18,7 +18,8 @@
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#define CONFIG_ASSERT_HELP
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#define CONFIG_CONSOLE_CMDHELP
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#define CONFIG_PANIC_HELP
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#define CONFIG_TASK_PROFILING
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#define CONFIG_TASK_PROFILING
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#define CONFIG_WATCHDOG_HELP
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/* Optional features */
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#define CONFIG_BATTERY_BQ20Z453
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@@ -44,7 +45,6 @@
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#ifdef PORT_TO_PIT
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/* TODO(rspangler): enable these features when they compile */
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#define CONFIG_LOW_POWER_IDLE
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#define CONFIG_WATCHDOG_HELP
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#endif
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#ifndef __ASSEMBLER__
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@@ -74,7 +74,8 @@
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/* Timer selection */
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#define TIM_CLOCK_MSB 3
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#define TIM_CLOCK_LSB 4
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#define TIM_CLOCK_LSB 9
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#define TIM_WATCHDOG 4
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/* GPIO signal list */
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enum gpio_signal {
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@@ -66,6 +66,7 @@
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/* Timer selection */
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#define TIM_CLOCK_MSB 3
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#define TIM_CLOCK_LSB 4
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#define TIM_WATCHDOG 1
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/* GPIO signal list */
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enum gpio_signal {
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@@ -67,6 +67,7 @@
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/* Timer selection */
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#define TIM_CLOCK_MSB 2
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#define TIM_CLOCK_LSB 4
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#define TIM_WATCHDOG 1
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/* ADC signal */
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enum adc_channel {
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@@ -16,21 +16,59 @@
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/* Divider to get microsecond for the clock */
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#define CLOCKSOURCE_DIVIDER (CPU_CLOCK / SECOND)
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#define TIM_WD_IRQ STM32_IRQ_TIM1_UP_TIM16
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#define TIM_WD 1 /* Timer to use for watchdog */
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/*
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* Trigger select mapping for slave timer from master timer. This is
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* unfortunately not very straightforward; there's no tidy way to do this
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* algorithmically. To avoid burning memory for a lookup table, use macros to
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* compute the offset. This also has the benefit that compilation will fail if
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* an unsupported master/slave pairing is used.
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*
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* Slave Master
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* 1 15 2 3 4 (STM32F100 only)
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* 2 9 10 3 4
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* 3 9 2 11 4
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* 4 10 2 3 9
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* 9 2 3 10 11 (STM32L15x only)
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* --------------------
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* ts = 0 1 2 3
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*/
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#define STM32_TIM_TS_SLAVE_1_MASTER_15 0
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#define STM32_TIM_TS_SLAVE_1_MASTER_2 1
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#define STM32_TIM_TS_SLAVE_1_MASTER_3 2
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#define STM32_TIM_TS_SLAVE_1_MASTER_4 3
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#define STM32_TIM_TS_SLAVE_2_MASTER_9 0
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#define STM32_TIM_TS_SLAVE_2_MASTER_10 1
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#define STM32_TIM_TS_SLAVE_2_MASTER_3 2
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#define STM32_TIM_TS_SLAVE_2_MASTER_4 3
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#define STM32_TIM_TS_SLAVE_3_MASTER_9 0
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#define STM32_TIM_TS_SLAVE_3_MASTER_2 1
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#define STM32_TIM_TS_SLAVE_3_MASTER_11 2
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#define STM32_TIM_TS_SLAVE_3_MASTER_4 3
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#define STM32_TIM_TS_SLAVE_4_MASTER_10 0
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#define STM32_TIM_TS_SLAVE_4_MASTER_2 1
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#define STM32_TIM_TS_SLAVE_4_MASTER_3 2
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#define STM32_TIM_TS_SLAVE_4_MASTER_9 3
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#define STM32_TIM_TS_SLAVE_9_MASTER_2 0
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#define STM32_TIM_TS_SLAVE_9_MASTER_3 1
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#define STM32_TIM_TS_SLAVE_9_MASTER_10 2
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#define STM32_TIM_TS_SLAVE_9_MASTER_11 3
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#define TSMAP1(slave, master) STM32_TIM_TS_SLAVE_ ## slave ## _MASTER_ ## master
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#define TSMAP(slave, master) TSMAP1(slave, master)
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/*
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* TIM_CLOCK_MSB and TIM_CLOCK_LSB must be defined per board. The available
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* values are 2, 3, and 4. This gives us flexibility to make any of the three
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* timer as a PWM source.
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* Timers are defined per board. This gives us flexibility to work around
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* timers which are dedicated to board-specific PWM sources.
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*/
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#define IRQ_TIM(n) STM32_CAT(STM32_IRQ_TIM, n, )
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#define IRQ_MSB IRQ_TIM(TIM_CLOCK_MSB)
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#define IRQ_LSB IRQ_TIM(TIM_CLOCK_LSB)
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#define IRQ_WD IRQ_TIM(TIM_WATCHDOG)
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enum {
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TIM_WD_BASE = STM32_TIM1_BASE,
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};
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/* TIM1 has fancy names for its IRQs; remap count-up IRQ for the macro above */
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#define STM32_IRQ_TIM1 STM32_IRQ_TIM1_UP_TIM16
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#define TIM_BASE(n) STM32_CAT(STM32_TIM, n, _BASE)
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#define TIM_WD_BASE TIM_BASE(TIM_WATCHDOG)
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static uint32_t last_deadline;
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@@ -123,6 +161,16 @@ static void __hw_clock_source_irq(void)
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DECLARE_IRQ(IRQ_MSB, __hw_clock_source_irq, 1);
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DECLARE_IRQ(IRQ_LSB, __hw_clock_source_irq, 1);
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void __hw_timer_enable_clock(int n)
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{
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if (n == 1) /* STM32F only */
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STM32_RCC_APB2ENR |= 1 << 11;
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else if (n >= 2 && n <= 7)
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STM32_RCC_APB1ENR |= 1 << (n - 2);
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else if (n >= 9 && n <= 11) /* STM32L only */
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STM32_RCC_APB2ENR |= 1 << (n - 7);
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}
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int __hw_clock_source_init(uint32_t start_t)
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{
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/*
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@@ -132,8 +180,8 @@ int __hw_clock_source_init(uint32_t start_t)
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*/
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/* Enable TIM_CLOCK_MSB and TIM_CLOCK_LSB clocks */
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STM32_RCC_APB1ENR |= (1 << (TIM_CLOCK_MSB - 2)) |
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(1 << (TIM_CLOCK_LSB - 2));
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__hw_timer_enable_clock(TIM_CLOCK_MSB);
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__hw_timer_enable_clock(TIM_CLOCK_LSB);
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/*
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* Timer configuration : Upcounter, counter disabled, update event only
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@@ -147,9 +195,11 @@ int __hw_clock_source_init(uint32_t start_t)
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*/
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STM32_TIM_CR2(TIM_CLOCK_MSB) = 0x0000;
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STM32_TIM_CR2(TIM_CLOCK_LSB) = 0x0020;
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/* TIM_CLOCK_MSB (slave mode) uses TIM_CLOCK_LSB as internal trigger */
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STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 | ((TIM_CLOCK_LSB - 1) << 4);
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STM32_TIM_SMCR(TIM_CLOCK_MSB) = 0x0007 |
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(TSMAP(TIM_CLOCK_MSB, TIM_CLOCK_LSB) << 4);
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STM32_TIM_SMCR(TIM_CLOCK_LSB) = 0x0000;
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/* Auto-reload value : 16-bit free-running counters */
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STM32_TIM_ARR(TIM_CLOCK_MSB) = 0xffff;
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STM32_TIM_ARR(TIM_CLOCK_LSB) = 0xffff;
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@@ -184,12 +234,7 @@ int __hw_clock_source_init(uint32_t start_t)
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return IRQ_LSB;
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}
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/*
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* We don't have TIM1 on STM32L, so don't support this function for now. TIM5
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* doesn't appear to exist in either variant, and TIM9 cannot be triggered as a
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* slave from TIM4. We could perhaps use TIM9 as our fast counter on STM32L.
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*/
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#if defined(CONFIG_WATCHDOG) && !defined(CHIP_VARIANT_stm32l15x)
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#ifdef CONFIG_WATCHDOG_HELP
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void watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
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{
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@@ -201,8 +246,8 @@ void watchdog_check(uint32_t excep_lr, uint32_t excep_sp)
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watchdog_trace(excep_lr, excep_sp);
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}
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void IRQ_HANDLER(TIM_WD_IRQ)(void) __attribute__((naked));
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void IRQ_HANDLER(TIM_WD_IRQ)(void)
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void IRQ_HANDLER(IRQ_WD)(void) __attribute__((naked));
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void IRQ_HANDLER(IRQ_WD)(void)
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{
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/* Naked call so we can extract raw LR and SP */
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asm volatile("mov r0, lr\n"
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@@ -215,9 +260,9 @@ void IRQ_HANDLER(TIM_WD_IRQ)(void)
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"pop {r0, lr}\n"
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"b task_resched_if_needed\n");
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}
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const struct irq_priority IRQ_BUILD_NAME(prio_, TIM_WD_IRQ, )
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const struct irq_priority IRQ_BUILD_NAME(prio_, IRQ_WD, )
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__attribute__((section(".rodata.irqprio")))
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= {TIM_WD_IRQ, 0}; /* put the watchdog at the highest
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= {IRQ_WD, 0}; /* put the watchdog at the highest
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priority */
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void hwtimer_setup_watchdog(void)
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@@ -225,11 +270,7 @@ void hwtimer_setup_watchdog(void)
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struct timer_ctlr *timer = (struct timer_ctlr *)TIM_WD_BASE;
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/* Enable clock */
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#if TIM_WD == 1
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STM32_RCC_APB2ENR |= 1 << 11;
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#else
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STM32_RCC_APB1ENR |= 1 << (TIM_WD - 2);
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#endif
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__hw_timer_enable_clock(TIM_WATCHDOG);
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/*
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* Timer configuration : Down counter, counter disabled, update
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@@ -238,7 +279,7 @@ void hwtimer_setup_watchdog(void)
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timer->cr1 = 0x0014 | (1 << 7);
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/* TIM (slave mode) uses TIM_CLOCK_LSB as internal trigger */
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timer->smcr = 0x0007 | ((TIM_CLOCK_LSB - 1) << 4);
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timer->smcr = 0x0007 | (TSMAP(TIM_WATCHDOG, TIM_CLOCK_LSB) << 4);
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/*
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* The auto-reload value is based on the period between rollovers for
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@@ -247,7 +288,7 @@ void hwtimer_setup_watchdog(void)
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* to obtain the number of times TIM_CLOCK_LSB can overflow before we
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* generate an interrupt.
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*/
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timer->arr = timer->cnt = WATCHDOG_PERIOD_MS * 1000 / (1 << 16);
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timer->arr = timer->cnt = WATCHDOG_PERIOD_MS * MSEC / (1 << 16);
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/* count on every TIM_CLOCK_LSB overflow */
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timer->psc = 0;
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@@ -262,7 +303,7 @@ void hwtimer_setup_watchdog(void)
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timer->cr1 |= 1;
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/* Enable timer interrupts */
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task_enable_irq(TIM_WD_IRQ);
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task_enable_irq(IRQ_WD);
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}
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void hwtimer_reset_watchdog(void)
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@@ -272,4 +313,4 @@ void hwtimer_reset_watchdog(void)
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timer->cnt = timer->arr;
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}
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#endif /* defined(CONFIG_WATCHDOG) && !defined(CHIP_VARIANT_stm32l15x) */
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#endif /* defined(CONFIG_WATCHDOG) */
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@@ -26,6 +26,13 @@ uint32_t __hw_clock_source_read(void);
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/* Override the current value of the hardware counter */
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void __hw_clock_source_set(uint32_t ts);
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/**
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* Enable clock to a timer.
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*
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* @param n Timer number to enable
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*/
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void __hw_timer_enable_clock(int n);
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/**
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* Initializes the hardware timer used to provide clock services, using the
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* specified start timer value.
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