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Add the SDRAM parameter header file.
Change-Id: I9d48b5c9222a50695df00694a97f8c52729657e7 BUG=None. TEST=None. Review URL: http://codereview.chromium.org/6602078 Patch from Peer Chen <pchen@nvidia.com>.
This commit is contained in:
Peer Chen
41
nvboot_bct.h
41
nvboot_bct.h
@@ -24,6 +24,7 @@
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#define INCLUDED_NVBOOT_BCT_H
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#include <sys/types.h>
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#include "nvboot_sdram_param.h"
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/**
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* Defines the number of 32-bit words in the customer_data area of the BCT.
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@@ -46,14 +47,18 @@
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*/
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#define NVBOOT_MAX_BOOTLOADERS 4
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#define NVBOOT_BCT_USED_DATA_SIZE 2052
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/**
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* Defines the maximum number of device parameter sets in the BCT.
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* The value must be equal to (1 << # of device straps)
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*/
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#define NVBOOT_BCT_MAX_PARAM_SETS 4
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/**
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* Defines the maximum number of SDRAM parameter sets in the BCT.
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* The value must be equal to (1 << # of SDRAM straps)
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*/
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#define NVBOOT_BCT_MAX_SDRAM_SETS 4
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/**
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* Defines the number of entries (bits) in the bad block table.
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* The consequences of changing its value are as follows. Using P as the
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@@ -99,6 +104,28 @@ typedef struct nvboot_hash_rec
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u_int32_t hash[NVBOOT_CMAC_AES_HASH_LENGTH];
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} nvboot_hash;
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/// Defines the params that can be configured for NAND devices.
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typedef struct nvboot_nand_params_rec{
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/**
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* Specifies the clock divider for the PLL_P 432MHz source.
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* If it is set to 18, then clock source to Nand controller is
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* 432 / 18 = 24MHz.
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*/
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u_int8_t clock_divider;
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/// Specifies the value to be programmed to Nand Timing Register 1
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u_int32_t nand_timing;
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/// Specifies the value to be programmed to Nand Timing Register 2
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u_int32_t nand_timing2;
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/// Specifies the block size in log2 bytes
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u_int8_t block_size_log2;
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/// Specifies the page size in log2 bytes
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u_int8_t page_size_log2;
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} nvboot_nand_params;
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/// Defines various data widths supported.
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typedef enum
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{
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@@ -143,7 +170,6 @@ typedef struct nvboot_sdmmc_params_rec
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* data width cannot be used at the chosen clock frequency.
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*/
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u_int8_t max_power_class_supported;
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u_int32_t reserved;
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} nvboot_sdmmc_params;
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typedef enum
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@@ -199,6 +225,8 @@ typedef struct nvboot_spiflash_params_rec
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* Defines the union of the parameters required by each device.
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*/
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typedef union{
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/// Specifies optimized parameters for NAND
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nvboot_nand_params nand_params;
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/// Specifies optimized parameters for eMMC and eSD
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nvboot_sdmmc_params sdmmc_params;
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/// Specifies optimized parameters for SPI NOR
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@@ -216,6 +244,9 @@ typedef enum
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/// Specifies a default (unset) value.
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nvboot_dev_type_none = 0,
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/// Specifies NAND.
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nvboot_dev_type_nand,
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/// Specifies SPI NOR.
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nvboot_dev_type_spi = 3,
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@@ -276,7 +307,8 @@ typedef struct nvboot_config_table_rec
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u_int32_t num_param_sets;
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nvboot_dev_type dev_type[NVBOOT_BCT_MAX_PARAM_SETS];
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nvboot_dev_params dev_params[NVBOOT_BCT_MAX_PARAM_SETS];
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u_int8_t bct_used_data[NVBOOT_BCT_USED_DATA_SIZE];
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u_int32_t num_sdram_sets;
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nvboot_sdram_params sdram_params[NVBOOT_BCT_MAX_SDRAM_SETS];
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nvboot_badblock_table badblock_table;
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u_int32_t bootloader_used;
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nv_bootloader_info bootloader[NVBOOT_MAX_BOOTLOADERS];
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@@ -285,5 +317,4 @@ typedef struct nvboot_config_table_rec
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u_int8_t reserved[NVBOOT_BCT_RESERVED_SIZE];
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} nvboot_config_table;
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/** @} */
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#endif /* #ifndef INCLUDED_NVBOOT_BCT_H */
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328
nvboot_sdram_param.h
Normal file
328
nvboot_sdram_param.h
Normal file
@@ -0,0 +1,328 @@
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/**
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* Copyright (c) 2011 NVIDIA Corporation. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/**
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* Defines the SDRAM parameter structure.
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*
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* Note that PLLM is used by EMC.
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*/
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#ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H
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#define INCLUDED_NVBOOT_SDRAM_PARAM_H
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#define NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS 27
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typedef enum
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{
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/// Specifies the memory type to be undefined
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nvboot_memory_type_none = 0,
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/// Specifies the memory type to be DDR SDRAM
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nvboot_memory_type_ddr,
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/// Specifies the memory type to be LPDDR SDRAM
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nvboot_memory_type_lpddr,
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/// Specifies the memory type to be DDR2 SDRAM
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nvboot_memory_type_ddr2,
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/// Specifies the memory type to be LPDDR2 SDRAM
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nvboot_memory_type_lpddr2,
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nvboot_memory_type_num,
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nvboot_memory_type_force32 = 0x7FFFFFF
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} nvboot_memory_type;
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/**
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* Defines the SDRAM parameter structure
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*/
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typedef struct nvboot_sdram_params_rec
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{
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/// Specifies the type of memory device
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nvboot_memory_type memory_type;
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/// Specifies the CPCON value for PllM
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u_int32_t pllm_charge_pump_setup_ctrl;
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/// Specifies the LPCON value for PllM
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u_int32_t pllm_loop_filter_setup_ctrl;
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/// Specifies the M value for PllM
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u_int32_t pllm_input_divider;
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/// Specifies the N value for PllM
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u_int32_t pllm_feedback_divider;
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/// Specifies the P value for PllM
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u_int32_t pllm_post_divider;
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/// Specifies the time to wait for PLLM to lock (in microseconds)
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u_int32_t pllm_stable_time;
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/// Specifies the divider for the EMC Clock Source
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u_int32_t emc_clock_divider;
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///
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/// Auto-calibration of EMC pads
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///
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/// Specifies the value for EMC_AUTO_CAL_INTERVAL
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u_int32_t emc_auto_cal_interval;
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/// Specifies the value for EMC_AUTO_CAL_CONFIG
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/// Note: Trigger bits are set by the SDRAM code.
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u_int32_t emc_auto_cal_config;
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/// Specifies the time for the calibration to
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/// stabilize (in microseconds)
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u_int32_t emc_auto_cal_wait;
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/// Specifies the time to wait after pin programming (in microseconds)
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/// Dram vendors require at least 200us.
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u_int32_t emc_pin_program_wait;
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///
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/// Timing parameters required for the SDRAM
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///
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/// Specifies the value for EMC_RC
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u_int32_t emc_rc;
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/// Specifies the value for EMC_RFC
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u_int32_t emc_rfc;
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/// Specifies the value for EMC_RAS
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u_int32_t emc_ras;
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/// Specifies the value for EMC_RP
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u_int32_t emc_rp;
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/// Specifies the value for EMC_R2W
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u_int32_t emc_r2w;
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/// Specifies the value for EMC_R2W
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u_int32_t emc_w2r;
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/// Specifies the value for EMC_R2P
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u_int32_t emc_r2p;
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/// Specifies the value for EMC_W2P
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u_int32_t emc_w2p;
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/// Specifies the value for EMC_RD_RCD
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u_int32_t emc_rd_rcd;
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/// Specifies the value for EMC_WR_RCD
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u_int32_t emc_wr_rcd;
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/// Specifies the value for EMC_RRD
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u_int32_t emc_rrd;
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/// Specifies the value for EMC_REXT
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u_int32_t emc_rext;
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/// Specifies the value for EMC_WDV
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u_int32_t emc_wdv;
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/// Specifies the value for EMC_QUSE
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u_int32_t emc_quse;
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/// Specifies the value for EMC_QRST
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u_int32_t emc_qrst;
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/// Specifies the value for EMC_QSAFE
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u_int32_t emc_qsafe;
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/// Specifies the value for EMC_RDV
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u_int32_t emc_rdv;
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/// Specifies the value for EMC_REFRESH
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u_int32_t emc_refresh;
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/// Specifies the value for EMC_BURST_REFRESH_NUM
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u_int32_t emc_burst_refresh_num;
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/// Specifies the value for EMC_PDEX2WR
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u_int32_t emc_pdex2wr;
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/// Specifies the value for EMC_PDEX2RD
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u_int32_t emc_pdex2rd;
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/// Specifies the value for EMC_PCHG2PDEN
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u_int32_t emc_pchg2pden;
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/// Specifies the value for EMC_ACT2PDEN
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u_int32_t emc_act2pden;
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/// Specifies the value for EMC_AR2PDEN
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u_int32_t emc_ar2pden;
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/// Specifies the value for EMC_RW2PDEN
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u_int32_t emc_rw2pden;
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/// Specifies the value for EMC_TXSR
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u_int32_t emc_txsr;
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/// Specifies the value for EMC_TCKE
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u_int32_t emc_tcke;
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/// Specifies the value for EMC_TFAW
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u_int32_t emc_tfaw;
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/// Specifies the value for EMC_TRPAB
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u_int32_t emc_trpab;
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/// Specifies the value for EMC_TCLKSTABLE
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u_int32_t emc_tclkstable;
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/// Specifies the value for EMC_TCLKSTOP
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u_int32_t emc_tclkstop;
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/// Specifies the value for EMC_TREFBW
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u_int32_t emc_trefbw;
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/// Specifies the value for EMC_QUSE_EXTRA
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u_int32_t emc_quse_extra;
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///
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/// FBIO configuration values
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///
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/// Specifies the value for EMC_FBIO_CFG1
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u_int32_t emc_fbio_cfg1;
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/// Specifies the value for EMC_FBIO_DQSIB_DLY
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u_int32_t emc_fbio_dqsib_dly;
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/// Specifies the value for EMC_FBIO_DQSIB_DLY_MSB
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u_int32_t emc_fbio_dqsib_dly_msb;
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/// Specifies the value for EMC_FBIO_QUSE_DLY
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u_int32_t emc_fbio_quse_dly;
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/// Specifies the value for EMC_FBIO_QUSE_DLY_MSB
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u_int32_t emc_fbio_quse_dly_msb;
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/// Specifies the value for EMC_FBIO_CFG5
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u_int32_t emc_fbio_cfg5;
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/// Specifies the value for EMC_FBIO_CFG6
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u_int32_t emc_fbio_cfg6;
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/// Specifies the value for EMC_FBIO_SPARE
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u_int32_t emc_fbio_spare;
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///
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/// MRS command values
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///
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/// Specifies the value for EMC_MRS
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u_int32_t emc_mrs;
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/// Specifies the value for EMC_EMRS
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u_int32_t emc_emrs;
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/// Specifies the first of a sequence of three values for EMC_MRW
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u_int32_t emc_mrw1;
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/// Specifies the second of a sequence of three values for EMC_MRW
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u_int32_t emc_mrw2;
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/// Specifies the third of a sequence of three values for EMC_MRW
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u_int32_t emc_mrw3;
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/// Specifies the EMC_MRW reset command value
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u_int32_t emc_mrw_reset_command;
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/// Specifies the EMC Reset wait time (in microseconds)
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u_int32_t emc_mrw_reset_ninit_wait;
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/// Specifies the value for EMC_ADR_CFG
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/// The same value is also used for MC_EMC_ADR_CFG
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u_int32_t emc_adr_cfg;
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/// Specifies the value for EMC_ADR_CFG_1
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u_int32_t emc_adr_cfg1;
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/// Specifies the value for MC_EMEM_CFG which holds the external memory
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/// size (in KBytes)
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/// EMEM_SIZE_KB must be <= (Device size in KB * Number of Devices)
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u_int32_t mc_emem_Cfg;
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/// Specifies the value for MC_LOWLATENCY_CONFIG
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/// Mainly for LL_DRAM_INTERLEAVE: Some DRAMs do not support interleave
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/// mode. If so, turn off this bit to get the correct low-latency path
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/// behavior. Reset is ENABLED.
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u_int32_t mc_lowlatency_config;
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/// Specifies the value for EMC_CFG
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u_int32_t emc_cfg;
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/// Specifies the value for EMC_CFG_2
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u_int32_t emc_cfg2;
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/// Specifies the value for EMC_DBG
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u_int32_t emc_dbg;
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/// Specifies the value for AHB_ARBITRATION_XBAR_CTRL.
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/// This is used to set the Memory Inid done
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u_int32_t ahb_arbitration_xbar_ctrl;
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/// Specifies the value for EMC_CFG_DIG_DLL
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/// Note: Trigger bits are set by the SDRAM code.
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u_int32_t emc_cfg_dig_dll;
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/// Specifies the value for EMC_DLL_XFORM_DQS
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u_int32_t emc_dll_xform_dqs;
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/// Specifies the value for EMC_DLL_XFORM_QUSE
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u_int32_t emc_dll_xform_quse;
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/// Specifies the delay after prgramming the PIN/NOP register during a
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/// WarmBoot0 sequence (in microseconds)
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u_int32_t warm_boot_wait;
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/// Specifies the value for EMC_CTT_TERM_CTRL
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u_int32_t emc_ctt_term_ctrl;
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/// Specifies the value for EMC_ODT_WRITE
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u_int32_t emc_odt_write;
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/// Specifies the value for EMC_ODT_WRITE
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u_int32_t emc_odt_read;
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/// Specifies the value for EMC_ZCAL_REF_CNT
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/// Only meaningful for LPDDR2. Set to 0 for all other memory types.
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u_int32_t emc_zcal_ref_cnt;
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/// Specifies the value for EMC_ZCAL_WAIT_CNT
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/// Only meaningful for LPDDR2. Set to 0 for all other memory types.
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u_int32_t emc_zcal_wait_cnt;
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/// Specifies the value for EMC_ZCAL_MRW_CMD
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/// Only meaningful for LPDDR2. Set to 0 for all other memory types.
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u_int32_t emc_zcal_mrw_cmd;
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/// Specifies the MRS command value for initilizing the mode register.
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u_int32_t emc_mrs_reset_dll;
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/// Specifies the MRW command for ZQ initialization of device 0
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u_int32_t emc_mrw_zq_init_dev0;
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/// Specifies the MRW command for ZQ initialization of device 1
|
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u_int32_t emc_mrw_zq_init_dev1;
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/// Specifies the wait time after programming a ZQ initialization
|
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/// command (in microseconds)
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u_int32_t emc_mrw_zq_init_wait;
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/// Specifies the wait time after sending an MRS DLL reset command
|
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/// (in microseconds)
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u_int32_t emc_mrs_reset_dll_wait;
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/// Specifies the first of two EMRS commands to initialize mode
|
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/// registers
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u_int32_t emc_emrs_emr2;
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/// Specifies the second of two EMRS commands to initialize mode
|
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/// registers
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u_int32_t emc_emrs_emr3;
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/// Specifies the EMRS command to enable the DDR2 DLL
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u_int32_t emc_emrs_ddr2_dll_enable;
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/// Specifies the MRS command to reset the DDR2 DLL
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u_int32_t emc_mrs_ddr2_dll_reset;
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/// Specifies the EMRS command to set OCD calibration
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u_int32_t emc_emrs_ddr2_ocd_calib;
|
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/// Specifies the wait between initializing DDR and setting OCD
|
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/// calibration (in microseconds)
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u_int32_t emc_ddr2_wait;
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///
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/// Clock trimmers
|
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///
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/// Specifies the value for EMC_CFG_CLKTRIM_0
|
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u_int32_t emc_cfg_clktrim0;
|
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/// Specifies the value for EMC_CFG_CLKTRIM_1
|
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u_int32_t emc_cfg_clktrim1;
|
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/// Specifies the value for EMC_CFG_CLKTRIM_2
|
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u_int32_t emc_cfg_clktrim2;
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///
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/// Pad controls
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///
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/// Specifies the value for PMC_DDR_PWR
|
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u_int32_t pmc_ddr_pwr;
|
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/// Specifies the value for APB_MISC_GP_XM2CFGAPADCTRL
|
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u_int32_t apb_misc_gp_xm2cfga_pad_ctrl;
|
||||
/// Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL
|
||||
u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl;
|
||||
/// Specifies the value for APB_MISC_GP_XM2CFGCPADCTRL2
|
||||
u_int32_t apb_misc_gp_xm2cfgc_pad_ctrl2;
|
||||
/// Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL
|
||||
u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl;
|
||||
/// Specifies the value for APB_MISC_GP_XM2CFGDPADCTRL2
|
||||
u_int32_t apb_misc_gp_xm2cfgd_pad_ctrl2;
|
||||
/// Specifies the value for APB_MISC_GP_XM2CLKCFGPADCTRL
|
||||
u_int32_t apb_misc_gp_xm2clkcfg_Pad_ctrl;
|
||||
/// Specifies the value for APB_MISC_GP_XM2COMPPADCTRL
|
||||
u_int32_t apb_misc_gp_xm2comp_pad_ctrl;
|
||||
/// Specifies the value for APB_MISC_GP_XM2VTTGENPADCTRL
|
||||
u_int32_t apb_misc_gp_xm2vttgen_pad_ctrl;
|
||||
|
||||
/// Specifies storage for arbitration configuration registers
|
||||
/// Data passed through to the Bootloader but not used by the Boot ROM
|
||||
u_int32_t arbitration_config[NVBOOT_BCT_SDRAM_ARB_CONFIG_WORDS];
|
||||
} nvboot_sdram_params;
|
||||
|
||||
#endif /* #ifndef INCLUDED_NVBOOT_SDRAM_PARAM_H */
|
||||
|
||||
Reference in New Issue
Block a user