ryu_sh_loader: Add board directory for load image

Ryu sensor hub has asymectric RO/RW images. The first one is very limited (not i2c master, no sensor drivers, gesture recognition). Image size is alter to offer more space for the RW firmware image, compiled with ryu_sh board. To write RO image and basic RW image: flashrom -V -p ec:type=sh,block=0x800 --fast-verify -w /tmp/ryu_sh_loader/ec.bin To write the expected RW image: flashrom -V -p ec:type=sh,block=0x800 --fast-verify -w -i EC_RW:/tmp/ryu_sh/ec.bin BRANCH=ToT BUG=chrome-os-partner:33908 CQ-DEPEND=CL:231970,CL:233233 TEST=load on Ryu, confirmed limited operation. Change-Id: Ib976e2b048935adfb9b2b072c071db5be2bc1c09 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/231984 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
2025-12-27 18:25:05 +00:00 · 2014-11-19 16:15:57 -08:00
parent 98a485bf43
commit 91ca05cf3a
14 changed files with 214 additions and 15 deletions
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -80,7 +80,8 @@ proj-%:
 	@echo "======= building $*"; \
 	$(MAKE) --no-print-directory BOARD=$* V=$(V)

-dis-y = $(out)/$(PROJECT).RO.dis $(out)/$(PROJECT).RW.dis
+dis-y = $(out)/$(PROJECT).RW.dis
+dis-$(CONFIG_FW_INCLUDE_RO) += $(out)/$(PROJECT).RO.dis
 dis: $(dis-y)

 hex-y = $(out)/$(PROJECT).RO.hex $(out)/$(PROJECT).RW.hex
@@ -159,7 +160,9 @@ $(out)/%.bin: $(out)/%.obj
 $(out)/%.spi.bin: $(out)/%.bin
 	$(call quiet,pack_package,PACK   )

-flat-y = $(out)/$(PROJECT).RO.flat $(out)/$(PROJECT).RW.flat
+flat-y = $(out)/$(PROJECT).RW.flat
+flat-$(CONFIG_FW_INCLUDE_RO) += $(out)/$(PROJECT).RO.flat
+
 deps += $(out)/firmware_image.lds.d $(flat-y:%.flat=%.lds.d)

 $(out)/%.obj: common/firmware_image.S $(out)/firmware_image.lds $(flat-y)
--- a/board/ryu_sh/board.c
+++ b/board/ryu_sh/board.c
@@ -18,12 +18,6 @@

 #include "gpio_list.h"

-/* Initialize board. */
-static void board_init(void)
-{
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
 	{GPIO_AP_IN_SUSPEND,  1, "SUSPEND_ASSERTED"},
--- a/board/ryu_sh/board.h
+++ b/board/ryu_sh/board.h
@@ -15,6 +15,14 @@
 #undef CONFIG_UART_CONSOLE
 #define CONFIG_UART_CONSOLE 1

+/*
+ * The RO firmware image size is limited to 40K to
+ * leave more space to the RW image.
+ */
+#undef CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_IMAGE_SIZE (40*1024)
+#undef CONFIG_FW_INCLUDE_RO
+
 /* By default, enable all console messages  */
 #define CC_DEFAULT     CC_ALL

@@ -46,6 +54,12 @@
 #define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3e
 #endif

+/*
+ * Write protect is active high, but given WP line is not implemented,
+ * the memory is not write protected.
+ */
+#define CONFIG_WP_ACTIVE_HIGH
+
 #ifndef __ASSEMBLER__

 /* Timer selection */
--- a/board/ryu_sh/gpio.inc
+++ b/board/ryu_sh/gpio.inc
@@ -31,7 +31,7 @@ GPIO(UART_RX,              A, 10, GPIO_OUT_LOW,  NULL)

 /* Needed to bypass flash write protection */
 UNIMPLEMENTED(ENTERING_RW)
-UNIMPLEMENTED(WP_L)
+UNIMPLEMENTED(WP)

 /*
 * I2C pins should be configured as inputs until I2C module is
--- a/board/ryu_sh_loader/Makefile
+++ b/board/ryu_sh_loader/Makefile
@@ -0,0 +1 @@
+../../Makefile
--- a/board/ryu_sh_loader/board.c
+++ b/board/ryu_sh_loader/board.c
@@ -0,0 +1,43 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* ryu sensor hub configuration */
+
+#include "common.h"
+#include "console.h"
+#include "driver/accelgyro_lsm6ds0.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "motion_sense.h"
+#include "power.h"
+#include "registers.h"
+#include "task.h"
+#include "util.h"
+
+#include "gpio_list.h"
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"slave",  I2C_PORT_SLAVE, 100,
+		GPIO_SLAVE_I2C_SCL, GPIO_SLAVE_I2C_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+void board_config_pre_init(void)
+{
+	/*
+	 *  enable SYSCFG clock:
+	 *  otherwise the SYSCFG peripheral is not clocked during the pre-init
+	 *  and the register write as no effect.
+	 */
+	STM32_RCC_APB2ENR |= 1 << 0;
+	/*
+	 * Remap USART DMA to match the USART driver
+	 * the DMA mapping is :
+	 *  Chan 4 : USART1_TX
+	 *  Chan 5 : USART1_RX
+	 */
+	STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
+}
--- a/board/ryu_sh_loader/board.h
+++ b/board/ryu_sh_loader/board.h
@@ -0,0 +1,65 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* ryu sensor board configuration */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/* the UART console is on USART1 (PA9/PA10) */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 1
+
+/*
+ * The firmware image size is limited to 40K to
+ * leave more space to the RW image.
+ */
+#undef CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_IMAGE_SIZE (40*1024)
+
+/* By default, enable all console messages  */
+#define CC_DEFAULT     CC_ALL
+
+/* Optional features */
+#undef CONFIG_EXTPOWER
+#undef CONFIG_HIBERNATE
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_I2C
+#define CONFIG_BOARD_PRE_INIT
+#undef  CONFIG_LID_SWITCH
+#undef CONFIG_CMD_POWER_AP
+#define CONFIG_POWER_COMMON
+#define CONFIG_VBOOT_HASH
+#undef CONFIG_WATCHDOG_HELP
+
+/* I2C ports configuration */
+#define I2C_PORT_SLAVE  0
+#define I2C_PORT_EC I2C_PORT_SLAVE
+
+/* slave address for host commands */
+#ifdef HAS_TASK_HOSTCMD
+#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR 0x3e
+#endif
+
+/*
+ * Write protect is active high, but given WP line is not implemented,
+ * the memory is not write protected.
+ */
+#define CONFIG_WP_ACTIVE_HIGH
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC     3
+
+#include "gpio_signal.h"
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __BOARD_H */
--- a/board/ryu_sh_loader/build.mk
+++ b/board/ryu_sh_loader/build.mk
@@ -0,0 +1,12 @@
+# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F072VBH6
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+board-y=board.o
--- a/board/ryu_sh_loader/ec.tasklist
+++ b/board/ryu_sh_loader/ec.tasklist
@@ -0,0 +1,22 @@
+/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' in the name of the task
+ * 'r' in the main routine of the task
+ * 'd' in an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
--- a/board/ryu_sh_loader/gpio.inc
+++ b/board/ryu_sh_loader/gpio.inc
@@ -0,0 +1,37 @@
+/* -*- mode:c -*-
+ *
+ * Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Interrupts */
+GPIO(AP_IN_SUSPEND,        E, 9,  GPIO_INT_BOTH,                   power_signal_interrupt)
+
+/* Outputs */
+GPIO(SH_EC_SIGNAL,         A, 7,  GPIO_OUT_LOW,  NULL)
+GPIO(SH_IRQ_L,             A, 11, GPIO_OUT_LOW,  NULL)
+
+/* Inputs */
+GPIO(LID_CLOSED,           A,  2, GPIO_INPUT,  NULL)
+GPIO(BASE_PRESENT,         A,  3, GPIO_INPUT,  NULL)
+
+#if 0
+/* Alternate functions */
+GPIO(UART_TX,              A,  9, GPIO_OUT_LOW,  NULL)
+GPIO(UART_RX,              A, 10, GPIO_OUT_LOW,  NULL)
+#endif
+
+/* Needed to bypass flash write protection */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP)
+
+/*
+ * I2C pins should be configured as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SLAVE_I2C_SCL,        B,  6, GPIO_INPUT,    NULL)
+GPIO(SLAVE_I2C_SDA,        B,  7, GPIO_INPUT,    NULL)
+
+ALTERNATE(A, 0x0600, 1, MODULE_UART,   0) /* USART1: PA9/PA10 */
+ALTERNATE(B, 0x00C0, 1, MODULE_I2C,    0) /* I2C SLAVE:PB6/7 */
--- a/chip/stm32/config-stm32f07x.h
+++ b/chip/stm32/config-stm32f07x.h
@@ -5,7 +5,7 @@

 /* Memory mapping */
 #define CONFIG_FLASH_BASE       0x08000000
-#define CONFIG_FLASH_PHYSICAL_SIZE 0x00020000
+#define CONFIG_FLASH_PHYSICAL_SIZE (128 * 1024)
 #define CONFIG_FLASH_SIZE       CONFIG_FLASH_PHYSICAL_SIZE
 #define CONFIG_FLASH_BANK_SIZE  0x1000
 #define CONFIG_FLASH_ERASE_SIZE 0x0800  /* erase bank size */
@@ -17,13 +17,13 @@
 #define CONFIG_RAM_BASE         0x20000000
 #define CONFIG_RAM_SIZE         0x00004000

-/* Size of one firmware image in flash */
-#define CONFIG_FW_IMAGE_SIZE    (64 * 1024)
+/* Size of the first firmware image in flash */
+#define CONFIG_FW_IMAGE_SIZE    (CONFIG_FLASH_SIZE / 2)

 #define CONFIG_FW_RO_OFF        0
 #define CONFIG_FW_RO_SIZE       (CONFIG_FW_IMAGE_SIZE - CONFIG_FW_PSTATE_SIZE)
-#define CONFIG_FW_RW_OFF        CONFIG_FW_IMAGE_SIZE
-#define CONFIG_FW_RW_SIZE       CONFIG_FW_IMAGE_SIZE
+#define CONFIG_FW_RW_OFF        (CONFIG_FW_RO_OFF + CONFIG_FW_IMAGE_SIZE)
+#define CONFIG_FW_RW_SIZE       (CONFIG_FLASH_SIZE - CONFIG_FW_IMAGE_SIZE)
 #define CONFIG_FW_WP_RO_OFF     CONFIG_FW_RO_OFF
 #define CONFIG_FW_WP_RO_SIZE    CONFIG_FW_IMAGE_SIZE

--- a/common/firmware_image.S
+++ b/common/firmware_image.S
@@ -14,8 +14,10 @@
 #define FW_IMAGE(sect) STRINGIFY(FW_FILE(OUTDIR,PROJECT,sect))

 /* Read Only firmware */
+#ifdef CONFIG_FW_INCLUDE_RO
 .section .image.RO, "ax"
 .incbin FW_IMAGE(RO)
+#endif

 /* Read Write firmware */
 .section .image.RW, "ax"
--- a/core/cortex-m/mpu.c
+++ b/core/cortex-m/mpu.c
@@ -147,7 +147,7 @@ int mpu_lock_ro_flash(void)
 int mpu_lock_rw_flash(void)
 {
 	return mpu_lock_region(REGION_FLASH_MEMORY, CONFIG_FW_RW_OFF,
-			       CONFIG_FW_IMAGE_SIZE, MPU_ATTR_FLASH_MEMORY);
+			       CONFIG_FW_RW_SIZE, MPU_ATTR_FLASH_MEMORY);
 }

 int mpu_pre_init(void)
--- a/include/config.h
+++ b/include/config.h
@@ -549,6 +549,12 @@
 #undef CONFIG_FW_WP_RO_OFF
 #undef CONFIG_FW_WP_RO_SIZE

+/*
+ * Board Image ec.bin contains a RO firmware.  If not defined, the image will
+ * only contain the RW firmware. The RO firmware comes from another board.
+ */
+#define CONFIG_FW_INCLUDE_RO
+
 /*****************************************************************************/
 /* Motion sensor based gesture recognition information */
 #undef CONFIG_GESTURE_DETECTION