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rowan: config SPI pins

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Configure B12/B13/B14/B15 as SPI pins.

BRANCH=master
BUG=chrome-os-partner:62673
TEST=EC_FIRMWARE=rowan emerge-rowan chromeos-ec

Change-Id: Ia7aad9ba0e15a8e6b623a8ae37f76db3f8f7c7a5
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/427563
Commit-Ready: Patrick Berny <pberny@chromium.org>
Tested-by: Patrick Berny <pberny@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
This commit is contained in:
Yidi Lin
2017-01-12 09:50:05 +08:00
committed by chrome-bot
parent 3a6431a309
commit 9316ec321a
1 changed files with 3 additions and 6 deletions
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9
board/rowan/board.c
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@@ -421,10 +421,8 @@ static void board_chipset_pre_init(void)
gpio_config_module(MODULE_SPI_MASTER, 1);
/* Set all four SPI pins to high speed */
/* pins D0/D1/D3/D4 */
STM32_GPIO_OSPEEDR(GPIO_D) |= 0x000003cf;
/* pins F6 */
STM32_GPIO_OSPEEDR(GPIO_F) |= 0x00003000;
/* pins B12/B13/B14/B15 */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
@@ -454,8 +452,7 @@ static void board_chipset_shutdown(void)
* Calling gpio_config_module sets disabled alternate function pins to
* GPIO_INPUT. But to prevent leakage we want to set GPIO_OUT_LOW
*/
gpio_set_flags_by_mask(GPIO_D, 0x1a, GPIO_OUT_LOW);
gpio_set_level(GPIO_SPI2_NSS, 0);
gpio_set_flags_by_mask(GPIO_B, 0xf000, GPIO_OUT_LOW);
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_chipset_shutdown, HOOK_PRIO_DEFAULT);