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nuc: Fixed flash layout issue for npcx

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Fixed flash layout issue for npcx

Modified drivers:
1. config_flash_layout.h: Fixed layout issue for npcx
2. flash_ec: add flashrom support for boards without JTAG in servo
connector

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: I0b9b679c52b8a8e2a26c278b5024d0350fb77338
Reviewed-on: https://chromium-review.googlesource.com/300392
Commit-Ready: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Mulin Chao
2015-09-17 21:21:00 +08:00
committed by chrome-bot
parent b03f92fbcc
commit 95ea672601
6 changed files with 98 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
chip/npcx/config_flash_layout.h
View File

@@ -45,14 +45,14 @@
#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE
/* RO firmware offset in flash */
#define CONFIG_RO_MEM_OFF CONFIG_RO_HDR_SIZE
#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RO_MEM_OFF 0
#define CONFIG_RO_SIZE CONFIG_FW_IMAGE_SIZE /* 96KB for RW FW */
/* RW firmware offset in flash */
#define CONFIG_RW_MEM_OFF CONFIG_RW_STORAGE_OFF
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE
#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE /* 96KB for RW FW */
/* The storage offset of ec.R*.flat which is used for CONFIG_CDRAM_ARCH */
/* The storage offset of ec.R*.flat which is used for firmware_image.lds */
#define CONFIG_RO_STORAGE_OFF CONFIG_RO_HDR_SIZE
#define CONFIG_RW_STORAGE_OFF 0

2
chip/npcx/spiflashfw/ec_npcxflash.c
View File

@@ -220,7 +220,7 @@ int sspi_flash_verify(int offset, int size, const char *data)
uint8_t *ptr_flash;
uint8_t *ptr_mram;
ptr_flash = (uint8_t *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
ptr_flash = (uint8_t *)(CONFIG_MAPPED_STORAGE_BASE + offset);
ptr_mram = (uint8_t *)data;
result = 1;

6
chip/npcx/system.c
View File

@@ -700,10 +700,12 @@ void system_jump_to_booter(void)
/* RO region FW */
if (IS_BIT_SET(NPCX_FWCTRL, NPCX_FWCTRL_RO_REGION)) {
flash_offset = CONFIG_RO_MEM_OFF;
flash_offset = CONFIG_EC_PROTECTED_STORAGE_OFF +
CONFIG_RO_STORAGE_OFF;
flash_used = CONFIG_RO_SIZE;
} else { /* RW region FW */
flash_offset = CONFIG_RW_MEM_OFF;
flash_offset = CONFIG_EC_WRITABLE_STORAGE_OFF +
CONFIG_RW_STORAGE_OFF;
flash_used = CONFIG_RW_SIZE;
}

14
common/firmware_image.lds.S
View File

@@ -14,7 +14,14 @@ MEMORY
SECTIONS
{
. = ALIGN(CONFIG_FLASH_BANK_SIZE);
#if defined(NPCX_RO_HEADER)
/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header
* or some struture which doesn't belong to FW */
.image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF\
) {
#else
.image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF) {
#endif
*(.image.RO)
} > FLASH =0xff
. = ALIGN(CONFIG_FLASH_BANK_SIZE);
@@ -25,7 +32,12 @@ SECTIONS
} > FLASH =0xff
. = ALIGN(CONFIG_FLASH_BANK_SIZE);
#endif
#ifdef CONFIG_EXTERNAL_STORAGE
#if defined(NPCX_RO_HEADER)
/* npcx uses *STORAGE_OFF to plan the layout of flash image */
.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF \
+ CONFIG_RW_STORAGE_OFF) {
#elif (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
/* This is applicable to ECs in which RO and RW execution is
mapped to the same location but we still have to generate an ec.bin with RO
and RW images at different Flash offset */

6
core/cortex-m/ec.lds.S
View File

@@ -25,11 +25,15 @@ MEMORY
* by booter.
*/
FLASH_HDR (rx) : ORIGIN = FW_OFF(RO_HDR), LENGTH = FW_SIZE(RO_HDR)
FLASH (rx) : ORIGIN = FW_OFF(SECTION) + FW_SIZE(RO_HDR), \
LENGTH = FW_SIZE(SECTION)
#else
FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
#endif
#ifdef CONFIG_SHAREDLIB
SHARED_LIB (rx) : ORIGIN = FW_OFF(SHAREDLIB), LENGTH = FW_SIZE_(SHAREDLIB)
#endif
FLASH (rx) : ORIGIN = FW_OFF(SECTION), LENGTH = FW_SIZE(SECTION)
IRAM (rw) : ORIGIN = CONFIG_RAM_BASE, LENGTH = CONFIG_RAM_SIZE
#ifdef CONFIG_EXTERNAL_STORAGE
CDRAM (rx) : \

117
util/flash_ec
View File

@@ -81,11 +81,15 @@ BOARDS_STM32_DFU=(
twinkie
)
BOARDS_NPCX=(
BOARDS_NPCX_JTAG=(
npcx_evb
npcx_evb_arm
)
BOARDS_NPCX_SPI=(
wheatley
)
BOARDS_NRF51=(
hadoken
)
@@ -341,6 +345,62 @@ function flash_openocd() {
die "Failed to program ${IMG}"
}
# helper function for using servo v2/3 with flashrom
function flash_flashrom() {
TOOL_PATH="${EC_DIR}/build/${BOARD}/util:/usr/sbin/:$PATH"
FLASHROM=$(PATH="${TOOL_PATH}" which flashrom)
FLASHROM_PARAM="-p ft2232_spi:type=servo-v2,port=B"
if [ ! -x "$FLASHROM" ]; then
die "no flashrom util found."
fi
SERIALNAME=$(${DUT_CONTROL_CMD} serialname | cut -d: -f2)
if [[ "$SERIALNAME" != "" ]] ; then
FLASHROM_PARAM="${FLASHROM_PARAM},serial=${SERIALNAME}"
fi
dut_control cold_reset:on
# Turn on SPI1 interface on servo for 3.3V SPI Flash Chip
dut_control spi1_vref:pp3300 spi1_buf_en:on spi1_buf_on_flex_en:on
SPI_SIZE=$(sudo ${FLASHROM} ${FLASHROM_PARAM} --get-size 2>/dev/null | tail -n 1)
IMG_SIZE=$(stat -c%s "$IMG")
PATCH_SIZE=$((${SPI_SIZE} - ${IMG_SIZE}))
# Temp image
T=/tmp/flash_spi_$$
if $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then
{ # Patch temp image up to SPI_SIZE
cat $IMG
if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
dd if=/dev/zero bs=${PATCH_SIZE} count=1 | tr '\0' '\377'
fi
} > $T
else
{ # Patch temp image up to SPI_SIZE
if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
dd if=/dev/zero bs=${PATCH_SIZE} count=1 | tr '\0' '\377'
fi
cat $IMG
} > $T
fi
sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
${FLASHROM} ${FLASHROM_PARAM} -w "${T}"
rm $T
# Turn off SPI1 interface on servo
dut_control spi1_vref:off spi1_buf_en:off spi1_buf_on_flex_en:off
# Do not save/restore servo settings
save=
}
function flash_stm32() {
TOOL_PATH="${EC_DIR}/build/${BOARD}/util:$PATH"
STM32MON=$(PATH="${TOOL_PATH}" which stm32mon)
@@ -418,7 +478,7 @@ function flash_nrf51() {
dut_control swd_reset:on swd_reset:off
}
function flash_npcx() {
function flash_npcx_jtag() {
IMG_PATH="${EC_DIR}/build/${BOARD}"
OCD_CHIP_CFG="npcx_chip.cfg"
if [ "${FLAGS_ro}" = ${FLAGS_TRUE} ] ; then
@@ -435,49 +495,12 @@ function flash_npcx() {
flash_openocd
}
function flash_npcx_spi() {
flash_flashrom
}
function flash_mec1322() {
TOOL_PATH="${EC_DIR}/build/${BOARD}/util:/usr/sbin/:$PATH"
FLASHROM=$(PATH="${TOOL_PATH}" which flashrom)
FLASHROM_PARAM="-p ft2232_spi:type=servo-v2,port=B"
if [ ! -x "$FLASHROM" ]; then
die "no flashrom util found."
fi
SERIALNAME=$(${DUT_CONTROL_CMD} serialname | cut -d: -f2)
if [[ "$SERIALNAME" != "" ]] ; then
FLASHROM_PARAM="${FLASHROM_PARAM},serial=${SERIALNAME}"
fi
dut_control cold_reset:on
# Turn on SPI1 interface on servo for 3.3V SPI Flash Chip
dut_control spi1_vref:pp3300 spi1_buf_en:on spi1_buf_on_flex_en:on
SPI_SIZE=$(sudo ${FLASHROM} ${FLASHROM_PARAM} --get-size 2>/dev/null | tail -n 1)
IMG_SIZE=$(stat -c%s "$IMG")
PATCH_SIZE=$((${SPI_SIZE} - ${IMG_SIZE}))
# Temp image
T=/tmp/flash_mec_$$
{ # Patch temp image up to SPI_SIZE
if [[ ${IMG_SIZE} -lt ${SPI_SIZE} ]] ; then
dd if=/dev/zero bs=${PATCH_SIZE} count=1 | tr '\0' '\377'
fi
cat $IMG
} > $T
sudo timeout -k 10 -s 9 "${FLAGS_timeout}" \
${FLASHROM} ${FLASHROM_PARAM} -w "${T}"
rm $T
# Turn off SPI1 interface on servo
dut_control spi1_vref:off spi1_buf_en:off spi1_buf_on_flex_en:off
# Do not save/restore servo settings
save=
flash_flashrom
}
if dut_control boot_mode 2>/dev/null ; then
@@ -502,8 +525,10 @@ elif $(in_array "${BOARDS_STM32[@]}" "${BOARD}"); then
CHIP="stm32"
elif $(in_array "${BOARDS_STM32_DFU[@]}" "${BOARD}"); then
CHIP="stm32_dfu"
elif $(in_array "${BOARDS_NPCX[@]}" "${BOARD}"); then
CHIP="npcx"
elif $(in_array "${BOARDS_NPCX_JTAG[@]}" "${BOARD}"); then
CHIP="npcx_jtag"
elif $(in_array "${BOARDS_NPCX_SPI[@]}" "${BOARD}"); then
CHIP="npcx_spi"
elif $(in_array "${BOARDS_NRF51[@]}" "${BOARD}"); then
CHIP="nrf51"
elif $(in_array "${BOARDS_MEC1322[@]}" "${BOARD}"); then