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stm32: force update generation during timer setup

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This corrects a small bug where by the UG bit in EGR was
not getting set, so the shadow registers were not being
reloaded as the comments suggest they should be.

This is really only a minor clean-up. The timer appears to
work fine with or without the patch.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
TEST=timerinfo appears sane on Snow

Change-Id: I637e2fc1f5dbfa1e70d33f96c8bf38ac57cc7b2c
Reviewed-on: https://gerrit.chromium.org/gerrit/26520
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Ready: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
David Hendricks
2012-06-29 17:29:32 -07:00
committed by Gerrit
parent 10873682a8
commit 95f11b09eb
1 changed files with 2 additions and 2 deletions
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4
chip/stm32/hwtimer.c
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@@ -123,8 +123,8 @@ int __hw_clock_source_init(uint32_t start_t)
STM32_TIM_PSC(4) = CLOCKSOURCE_DIVIDER - 1;
/* Reload the pre-scaler */
STM32_TIM_EGR(3) = 0x0000;
STM32_TIM_EGR(4) = 0x0000;
STM32_TIM_EGR(3) = 0x0001;
STM32_TIM_EGR(4) = 0x0001;
/* setup the overflow interrupt on TIM3 */
STM32_TIM_DIER(3) = 0x0001;