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glkrvp: Enable switches

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BUG=b:64491401
BRANCH=glkrvp
TEST=mmapinfo is updated when lidopen & lidclose are performed
     SCI/SMI gpios toggle

Change-Id: I93f1ae2cc8dbc389b3e870b49d5ee2bfff503451
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/606892
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Vijay Hiremath
2017-04-20 18:16:55 -07:00
committed by chrome-bot
parent 67644782eb
commit 97fe22e8d5
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/glkrvp/board.h
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@@ -65,6 +65,7 @@
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_S0IX
#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* EC */
#define CONFIG_BOARD_VERSION
@@ -99,7 +100,6 @@
/* EC exclude modules */
#undef CONFIG_ADC
#undef CONFIG_PECI
#undef CONFIG_SWITCH
#undef CONFIG_WATCHDOG
#ifndef __ASSEMBLER__

2
board/glkrvp/gpio.inc
View File

@@ -19,6 +19,7 @@ GPIO_INT(ALL_SYS_PGOOD, PIN(7, 2), GPIO_INT_BOTH, power_signal_interrupt) /* PM
GPIO_INT(POWER_BUTTON_L, PIN(A, 6), GPIO_INT_BOTH, power_button_interrupt) /* MECH_PWR_BTN_ODL */
GPIO_INT(LID_OPEN, PIN(0, 3), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt) /* SMC_LID */
GPIO_INT(AC_PRESENT, PIN(D, 2), GPIO_INT_BOTH, extpower_interrupt) /* ACOK_OD from ISL9238 */
GPIO_INT(WP_L, PIN(9, 3), GPIO_INT_BOTH | GPIO_SEL_1P8V, switch_interrupt) /* EC_WP_ODL */
GPIO(PCH_SMI_L, PIN(C, 6), GPIO_ODR_HIGH) /* EC_SMI_ODL */
GPIO(PCH_SCI_L, PIN(7, 6), GPIO_ODR_HIGH) /* EC_SCI_ODL */
@@ -93,7 +94,6 @@ GPIO(NC_D3, PIN(D, 3), GPIO_INPUT)
GPIO(NC_E7, PIN(E, 7), GPIO_INPUT)
/* Unused pins: VSPI 3.3V or 1.8V & Interruptable */
GPIO(NC_93, PIN(9, 3), GPIO_INPUT)
GPIO(NC_94, PIN(9, 4), GPIO_INPUT)
GPIO(NC_95, PIN(9, 5), GPIO_INPUT)