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zoombini: cannonlake: Add 5V power good signal.

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The 5V power good signal is being removed from the PMIC power good tree,
however, if the 5V power good is not asserted, we should not try booting
to S0.  This is because the 1050_STG rail load switch is powered off of
the 5V rail.

Since wireless power control is being moved to the AP, these pins are now
repurposed to control the PMIC enable and for the 5V power good signal.

This commit adds the 5V power good pin to the EC and makes it a required
power signal for S0.

BUG=b:66000679
BRANCH=None
TEST=make -j buildall
TEST=flash zoombini;  Verify EC boots up okay.

Change-Id: I8924320030a00b8808aea27fb668451e6e41d590
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/736312
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Aseda Aboagye
2017-10-24 12:55:09 -07:00
committed by chrome-bot
parent de63c62822
commit 9b28fe366e
4 changed files with 5 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/zoombini/board.c
View File

@@ -89,6 +89,7 @@ const struct power_signal_info power_signal_list[] = {
{GPIO_PCH_SLP_SUS_L, POWER_SIGNAL_ACTIVE_HIGH, "SLP_SUS_DEASSERTED"},
{GPIO_RSMRST_L_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "RSMRST_L_PGOOD"},
{GPIO_PMIC_DPWROK, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_DPWROK"},
{GPIO_PP5000_PGOOD, POWER_SIGNAL_ACTIVE_HIGH, "PP5000_A_PGOOD"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);

5
board/zoombini/board.h
View File

@@ -105,10 +105,6 @@
#define PD_POWER_SUPPLY_TURN_ON_DELAY 30000 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 250000 /* us */
#define CONFIG_WIRELESS
#define WIRELESS_GPIO_WLAN_POWER GPIO_EN_PP3300_WLAN
#define WIRELESS_GPIO_WWAN GPIO_EN_PP3300_WWAN
/* I2C Ports */
#define I2C_PORT_BATTERY I2C_PORT_POWER
#define I2C_PORT_CHARGER I2C_PORT_POWER
@@ -154,6 +150,7 @@ enum power_signal {
X86_SLP_SUS_DEASSERTED,
X86_RSMRST_L_PGOOD,
X86_PMIC_DPWROK,
PP5000_PGOOD,
POWER_SIGNAL_COUNT
};

3
board/zoombini/gpio.inc
View File

@@ -28,12 +28,11 @@ GPIO_INT(PCH_SLP_SUS_L, PIN(D, 4), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signa
GPIO_INT(RSMRST_L_PGOOD, PIN(E, 2), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PMIC_DPWROK, PIN(F, 4), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PMIC_INT_L, PIN(D, 5), GPIO_INT_FALLING | GPIO_PULL_UP, power_signal_interrupt)
GPIO_INT(PP5000_PGOOD, PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt)
/* Power Enables. */
GPIO(EN_PP3300_DSW, PIN(6, 0), GPIO_OUT_HIGH)
GPIO(EN_PP3300_TRACKPAD, PIN(B, 7), GPIO_OUT_LOW)
GPIO(EN_PP3300_WLAN, PIN(C, 0), GPIO_OUT_LOW)
GPIO(EN_PP3300_WWAN, PIN(D, 7), GPIO_OUT_LOW)
GPIO(EN_PP5000, PIN(7, 3), GPIO_OUT_LOW)
GPIO(ENTERING_RW, PIN(E, 1), GPIO_OUT_LOW)

3
power/cannonlake.h
View File

@@ -19,7 +19,8 @@
#define IN_PGOOD_ALL_CORE POWER_SIGNAL_MASK(X86_PMIC_DPWROK)
#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED | \
POWER_SIGNAL_MASK(PP5000_PGOOD))
#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED