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Cr50: Removed Reef EVT workarounds

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- changed the pad assignment for plt_rst_l from DIOA13 to DIOM3;
- removed the board property used to keep uart rx disabled, Uart0 is
  now enabled by default on Cr50.
- removed resetting fallback counter on USB updates for reef boards,
  they are going to use the same mechanism as kevin and gru.

BRANCH=none
BUG=chrome-os-partner:56540
TEST=Tested on Reef Board ID 1 and Gru Board ID 1. Verfied that
     plt_rst_l signal is being detected and that there are no
     interrupt storms related to not having a pullup resistor on the
     uart rx line. Verified that both platforms successfully boot into
     chrome OS using cr50 TPM.

Change-Id: I300a0c75e60acbecf93500b46aced303955a192a
Signed-off-by: Scott <scollyer@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/391140
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This commit is contained in:
Scott
2016-09-30 09:37:24 -07:00
committed by chrome-bot
parent e3a34da55b
commit 9cd10a5a47
4 changed files with 13 additions and 63 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
board/cr50/board.c
View File

@@ -129,17 +129,11 @@ void pmu_wakeup_interrupt(void)
* configured to wake on low and the signal is low, then call
* sys_rst_asserted
*/
/*
* TODO(crosbug.com/p/56540): When plt_rst_l is connected to
* DIOM3, need to change DIOA13 below to DIOM3 so that
* the correct wake on low setting is being checked.
*/
plt_rst_asserted = board_properties & BOARD_USE_PLT_RESET ?
!gpio_get_level(GPIO_PLT_RST_L) : 0;
if ((!gpio_get_level(GPIO_SYS_RST_L_IN) &&
GREAD_FIELD(PINMUX, EXITINV0, DIOM0)) || (plt_rst_asserted
&& GREAD_FIELD(PINMUX, EXITINV0, DIOA13)))
&& GREAD_FIELD(PINMUX, EXITINV0, DIOM3)))
sys_rst_asserted(GPIO_SYS_RST_L_IN);
}
@@ -191,18 +185,13 @@ void board_configure_deep_sleep_wakepins(void)
* rising edge of this signal.
*/
if (system_get_board_properties() & BOARD_USE_PLT_RESET) {
/*
* TODO(crosbug.com/p/56540): When plt_rst_l is connected to
* DIOM3, need to change DIOA13 below to DIOM3 so that
* the correct pin is being configured.
*/
/* Disable sys_rst_l as a wake pin */
GWRITE_FIELD(PINMUX, EXITEN0, DIOA13, 0);
GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 0);
/* Reconfigure and reenable it. */
GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA13, 1); /* edge sensitive */
GWRITE_FIELD(PINMUX, EXITINV0, DIOA13, 0); /* wake on high */
GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 1); /* edge sensitive */
GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 0); /* wake on high */
/* enable powerdown exit */
GWRITE_FIELD(PINMUX, EXITEN0, DIOA13, 1);
GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
}
}
@@ -268,30 +257,20 @@ static void configure_board_specific_gpios(void)
if (system_get_board_properties() & BOARD_NEEDS_SYS_RST_PULL_UP)
GWRITE_FIELD(PINMUX, DIOM0_CTL, PU, 1);
/*
* TODO(crosbug.com/p/56540): Need to connect platform reset to DI0A13
* for current Reef boards. This function is a no-op for Kevin/Gru. When
* platform reset is moved to DIOM3 in HW, then need change to
* GC_PINMUX_DIOM3_SEL and DIOM3_CTL respectively. In addition,
* uncomment the 3 GRWITE() lines for enabling wake on falling
* edge. Note that the DIO_WAKE_FALLING config is not required for
* DIOA13 as the default for this pad is for uart which already includes
* this option for the pminmux setting.
*/
/* Connect PLT_RST_L signal to the pinmux */
if (system_get_board_properties() & BOARD_USE_PLT_RESET) {
/* Signal using GPIO1 pin 10 for DIOA13 */
GWRITE(PINMUX, GPIO1_GPIO10_SEL, GC_PINMUX_DIOA13_SEL);
GWRITE(PINMUX, GPIO1_GPIO10_SEL, GC_PINMUX_DIOM3_SEL);
/* Enbale the input */
GWRITE_FIELD(PINMUX, DIOA13_CTL, IE, 1);
GWRITE_FIELD(PINMUX, DIOM3_CTL, IE, 1);
/* Set power down for the equivalent of DIO_WAKE_FALLING */
/* Set to be edge sensitive */
/* GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 1); */
GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 1);
/* Select failling edge polarity */
/* GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1); */
GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1);
/* Enable powerdown exit on DIOM3 */
/* GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1); */
GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
}
}
@@ -713,17 +692,6 @@ void system_init_board_properties(void)
properties |= BOARD_SLAVE_CONFIG_I2C;
/* One PHY is connected to the AP */
properties |= BOARD_USB_AP;
/*
* TODO(crosbug.com/p/56540): enable UART0 RX on Reef.
* Early reef boards dont have the necessary pullups on
* UART0RX so disable it until that is fixed.
*/
properties |= BOARD_DISABLE_UART0_RX;
/*
* Use receiving a usb set address request as a
* benchmark for marking the updated image as good.
*/
properties |= BOARD_MARK_UPDATE_ON_USB_REQ;
/*
* Platform reset is present and will need to be
* configured as a an falling edge interrupt.

13
chip/g/uartn.c
View File

@@ -112,19 +112,10 @@ void uartn_enable_interrupt(int uart)
}
/* Enable TX and RX. Disable HW flow control and loopback */
void uartn_enable(int uart)
{
/* Enable UART TX */
GR_UART_CTRL(uart) = 0x01;
/* TODO(crosbug.com/p/56540): Remove this when UART0_RX works everywhere */
#if defined(BOARD_CR50) && !defined(SECTION_IS_RO)
if (!uart && (system_get_board_properties() & BOARD_DISABLE_UART0_RX))
return;
#endif
GR_UART_CTRL(uart) |= 0x02;
/* Enable TX and RX. Disable HW flow control and loopback. */
GR_UART_CTRL(uart) = 0x03;
}
/* Disable TX, RX, HW flow control, and loopback */

6
chip/g/usb.c
View File

@@ -732,12 +732,6 @@ static int handle_setup_with_no_data_stage(enum table_case tc,
CPRINTS("SETAD 0x%02x (%d)", set_addr, set_addr);
print_later("SETAD 0x%02x (%d)", set_addr, set_addr, 0, 0, 0);
device_state = DS_ADDRESS;
#ifdef BOARD_CR50
/* TODO(crosbug.com/p/56540): Remove when no longer needed */
if (!processed_update_counter && system_get_board_properties() &
BOARD_MARK_UPDATE_ON_USB_REQ)
system_process_retry_counter();
#endif
processed_update_counter = 1;
break;

5
include/system.h
View File

@@ -483,14 +483,11 @@ int system_process_retry_counter(void);
void system_clear_retry_counter(void);
/* Board properties options */
/* Board properties options. A gap is left for backwards compatibility. */
#define BOARD_SLAVE_CONFIG_SPI (1 << 0) /* Slave SPI interface */
#define BOARD_SLAVE_CONFIG_I2C (1 << 1) /* Slave I2C interface */
#define BOARD_USB_AP (1 << 2) /* One of the PHYs is */
/* connected to the AP */
#define BOARD_DISABLE_UART0_RX (1 << 3) /* Disable UART0 RX */
#define BOARD_MARK_UPDATE_ON_USB_REQ (1 << 4) /* update is good once the */
/* controller gets a request */
/* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
#define BOARD_NEEDS_SYS_RST_PULL_UP (1 << 5) /* Add a pullup to sys_rst_l */
#define BOARD_USE_PLT_RESET (1 << 6) /* Platform reset exists */