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Cr50: Fix USB two-stage control transfers
This cleans up a great deal of flakiness that we've seen on the USB for a long time. I was misinterpreting and/or misimplementing some of the documentation. This seems to make all the difference. BUG=chrome-os-partner:50370 BRANCH=none CQ-DEPEND=CL:328979,CL:*249229 TEST=make buildall, and test on Cr50 Before this CL, the USB connection would only work on USB2.0 buses, connected directly to my workstation. With this CL, it works on USB2.0, USB3.0, through hubs, etc. Yay! Change-Id: Icfa1910bf34f73332e2f8fc4f0d6789541549493 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329262 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
committed by
chrome-bot
parent
4f15d2189f
commit
a58c24ee37
11
chip/g/usb.c
11
chip/g/usb.c
@@ -893,11 +893,9 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
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case NO_DATA_STAGE:
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if (intr_on_in && (diepint & DIEPINT_XFERCOMPL)) {
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print_later("Status phase complete", 0, 0, 0, 0, 0);
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print_later("IN descriptor processed", 0, 0, 0, 0, 0);
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/* Let the IN proceed */
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GR_USB_DIEPCTL(0) = DXEPCTL_EPENA;
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/* We've already prepared the OUT descriptor. */
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what_am_i_doing = WAITING_FOR_SETUP_PACKET;
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}
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/* Done unless we got an OUT interrupt */
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@@ -906,6 +904,8 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
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if (tc == TABLE_CASE_B) {
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print_later("IN has been detected...", 0, 0, 0, 0, 0);
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/* Let the IN proceed */
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GR_USB_DIEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
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/* Reenable the previously prepared OUT descriptor. */
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GR_USB_DOEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
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break;
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@@ -920,8 +920,9 @@ static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
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}
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}
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/* Some other kind of OUT interrupt instead. */
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report_error(tc);
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/* Anything else means get ready for a Setup packet */
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print_later("Status phase complete. Maybe.",
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0, 0, 0, 0, 0);
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expect_setup_packet();
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break;
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}
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