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nrf51: add the watchdog registers.

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The definitions for the watchdog registers are needed for hard reset.

BRANCH=NONE
BUG=None
TEST=make buildall -j

Change-Id: Ief73b98fbe6fc198c3eda28394e76bdf05568fef
Signed-off-by: Myles Watson <mylesgw@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/242900
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Myles Watson
2015-01-22 08:42:22 -08:00
committed by ChromeOS Commit Bot
parent 35c00bf3d9
commit ad06ead062
1 changed files with 30 additions and 0 deletions
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30
chip/nrf51/registers.h
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@@ -354,6 +354,36 @@
#define NRF51_TIMER0_BITMODE_32 3
/*
* Watchdog Timer (WDT)
*/
#define NRF51_WDT_BASE 0x40010000
/* Tasks */
#define NRF51_WDT_START REG32(NRF51_WDT_BASE + 0x000)
/* Events */
#define NRF51_WDT_TIMEOUT REG32(NRF51_WDT_BASE + 0x100)
/* Registers */
#define NRF51_WDT_INTENSET REG32(NRF51_WDT_BASE + 0x304)
#define NRF51_WDT_INTENCLR REG32(NRF51_WDT_BASE + 0x308)
#define NRF51_WDT_RUNSTATUS REG32(NRF51_WDT_BASE + 0x400)
#define NRF51_WDT_REQSTATUS REG32(NRF51_WDT_BASE + 0x404)
#define NRF51_WDT_CRV REG32(NRF51_WDT_BASE + 0x504)
#define NRF51_WDT_RREN REG32(NRF51_WDT_BASE + 0x508)
#define NRF51_WDT_CONFIG REG32(NRF51_WDT_BASE + 0x50C)
#define NRF51_WDT_RR(n) REG32(NRF51_WDT_BASE + 0x600 + ((n) * 4))
#define NRF51_WDT_POWER REG32(NRF51_WDT_BASE + 0xFFC)
/* Bitfields */
#define NRF51_WDT_RUNSTATUS_RUNNING 1
#define NRF51_WDT_REQSTATUS_BIT(n) (1<<(n))
#define NRF51_WDT_RREN_BIT(n) (1<<(n))
#define NRF51_WDT_CONFIG_SLEEP_PAUSE 0
#define NRF51_WDT_CONFIG_SLEEP_RUN 1
#define NRF51_WDT_CONFIG_HALT_PAUSE (0<<4)
#define NRF51_WDT_CONFIG_HALT_RUN (1<<4)
#define NRF51_WDT_RELOAD_VAL 0x6E524635
/*
* GPIO
*/