eve_fp: remove board

fp is dead, long life to fp.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=b:72360575
TEST=make buildall

Change-Id: Idccb953044018e24d14b6ef1dbf69766fb9b58ab
Reviewed-on: https://chromium-review.googlesource.com/880954
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Vincent Palatin
2018-01-23 15:03:31 +01:00
committed by chrome-bot
parent 04a9dfe645
commit adeb276aa6
6 changed files with 1 additions and 181 deletions

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@@ -1,58 +0,0 @@
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "spi.h"
#include "system.h"
#include "task.h"
#include "registers.h"
#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
static void ap_deferred(void)
{
if (gpio_get_level(GPIO_SLP_S3_L)) {
/* S0 */
gpio_set_flags(GPIO_EC_INT_L, GPIO_ODR_HIGH | GPIO_PULL_UP);
hook_notify(HOOK_CHIPSET_RESUME);
} else {
/* S3 */
gpio_set_flags(GPIO_EC_INT_L, GPIO_INPUT);
hook_notify(HOOK_CHIPSET_SUSPEND);
}
}
DECLARE_DEFERRED(ap_deferred);
void slp_event(enum gpio_signal signal)
{
hook_call_deferred(&ap_deferred_data, 0);
}
#include "gpio_list.h"
/* SPI devices */
const struct spi_device_t spi_devices[] = {
/* Fingerprint sensor */
{ CONFIG_SPI_FP_PORT, 1, GPIO_SPI3_NSS }
};
const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
/* Initialize board-specific configuraiton */
static void board_init(void)
{
/* Set all SPI master signal pins to very high speed: pins B3/B4/B5 */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000fc0;
/* Enable clocks to SPI3 module (master) */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI3;
/* Enable interrupt on SLP_S3_L */
gpio_enable_interrupt(GPIO_SLP_S3_L);
/* enable the SPI slave interface if the PCH is up */
hook_call_deferred(&ap_deferred_data, 0);
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);

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@@ -1,57 +0,0 @@
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Fingerprint microcontroller configuration */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
#define CONFIG_SYSTEM_UNLOCKED
/* Serial console */
#define CONFIG_UART_CONSOLE 1
#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
#define CONFIG_UART_TX_DMA_PH 2
/* Optional features */
#define CONFIG_CMD_SPI_XFER
#define CONFIG_HOST_COMMAND_STATUS
#undef CONFIG_LID_SWITCH
#define CONFIG_MKBP_EVENT
#define CONFIG_FPU
#define CONFIG_PRINTF_LEGACY_LI_FORMAT
#define CONFIG_SPI
#define CONFIG_SPI_MASTER
#define CONFIG_STM_HWTIMER32
#define CONFIG_WATCHDOG_HELP
/* Fingerprint configuration */
#define CONFIG_SPI_FP_PORT 1 /* SPI3: second SPI master port */
#define CONFIG_FP_SENSOR_FPC1145
#define CONFIG_CMD_FPSENSOR_DEBUG
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_WATCHDOG 16
/*
* PLL configuration for 80Mhz:
* SYSCLK = HSE * n/m/r = 16 * 10 / 2 = 80 Mhz
*/
#undef STM32_PLLM
#define STM32_PLLM 1
#undef STM32_PLLN
#define STM32_PLLN 10
#undef STM32_PLLR
#define STM32_PLLR 2
#ifndef __ASSEMBLER__
#include "gpio_signal.h"
void fps_event(enum gpio_signal signal);
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

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@@ -1,12 +0,0 @@
# Copyright 2017 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicroelectronics STM32L442KC
CHIP:=stm32
CHIP_FAMILY:=stm32l4
CHIP_VARIANT:=stm32l442
board-y=board.o

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@@ -1,24 +0,0 @@
/* Copyright 2017 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(FPSENSOR, fp_task, NULL, 4096) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)

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@@ -1,28 +0,0 @@
/*
* Copyright 2017 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(FPS_INT, PIN(A, 2), GPIO_INT_RISING, fps_event)
GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INPUT, spi_event)
GPIO_INT(SLP_S3_L, PIN(A, 11), GPIO_INT_BOTH, slp_event)
/* Outputs */
GPIO(EC_INT_L, PIN(A, 1), GPIO_INPUT) /* Enabled when PCH is up */
GPIO(FP_RST_ODL, PIN(A, 3), GPIO_ODR_LOW)
GPIO(SPI3_NSS, PIN(A, 15), GPIO_OUT_HIGH)
GPIO(WP_L, PIN(B, 7), GPIO_INPUT)
/* Unimplemented signals which we need to emulate */
UNIMPLEMENTED(ENTERING_RW)
/* USART1: PA9/10 */
ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_F7, MODULE_UART, 0)
/* SPI1 slave from PCH: PA4/5/6/7 */
ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_F5, MODULE_SPI, 0)
/* SPI3 master to sensor: PB3/4/5 */
ALTERNATE(PIN_MASK(B, 0x0038), GPIO_ALT_F6, MODULE_SPI_MASTER, 0)

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@@ -60,7 +60,6 @@ BOARDS_STM32=(
chell_pd
coffeecake
elm
eve_fp
glados_pd
hammer
jerry
@@ -453,7 +452,7 @@ function servo_ec_uart() {
case "${BOARD}" in
oak_pd|samus_pd|strago_pd ) MCU="usbpd" ;;
chell_pd|glados_pd ) MCU="usbpd" ;;
eve_fp|meowth_fp ) MCU="usbpd" ;;
meowth_fp ) MCU="usbpd" ;;
dingdong|hoho|twinkie ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;
*) MCU="ec" ;;
esac