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eve_fp: remove board
fp is dead, long life to fp. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575 TEST=make buildall Change-Id: Idccb953044018e24d14b6ef1dbf69766fb9b58ab Reviewed-on: https://chromium-review.googlesource.com/880954 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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adeb276aa6
@@ -1,58 +0,0 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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#include "common.h"
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#include "console.h"
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#include "gpio.h"
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#include "hooks.h"
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#include "spi.h"
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#include "system.h"
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#include "task.h"
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#include "registers.h"
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#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
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static void ap_deferred(void)
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{
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if (gpio_get_level(GPIO_SLP_S3_L)) {
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/* S0 */
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gpio_set_flags(GPIO_EC_INT_L, GPIO_ODR_HIGH | GPIO_PULL_UP);
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hook_notify(HOOK_CHIPSET_RESUME);
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} else {
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/* S3 */
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gpio_set_flags(GPIO_EC_INT_L, GPIO_INPUT);
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hook_notify(HOOK_CHIPSET_SUSPEND);
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}
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}
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DECLARE_DEFERRED(ap_deferred);
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void slp_event(enum gpio_signal signal)
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{
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hook_call_deferred(&ap_deferred_data, 0);
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}
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#include "gpio_list.h"
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/* SPI devices */
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const struct spi_device_t spi_devices[] = {
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/* Fingerprint sensor */
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{ CONFIG_SPI_FP_PORT, 1, GPIO_SPI3_NSS }
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};
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const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
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/* Initialize board-specific configuraiton */
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static void board_init(void)
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{
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/* Set all SPI master signal pins to very high speed: pins B3/B4/B5 */
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STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000fc0;
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/* Enable clocks to SPI3 module (master) */
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STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI3;
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/* Enable interrupt on SLP_S3_L */
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gpio_enable_interrupt(GPIO_SLP_S3_L);
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/* enable the SPI slave interface if the PCH is up */
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hook_call_deferred(&ap_deferred_data, 0);
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}
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DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
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@@ -1,57 +0,0 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Fingerprint microcontroller configuration */
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#ifndef __CROS_EC_BOARD_H
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#define __CROS_EC_BOARD_H
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#define CONFIG_SYSTEM_UNLOCKED
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/* Serial console */
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#define CONFIG_UART_CONSOLE 1
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#define CONFIG_UART_TX_DMA_CH STM32_DMAC_USART1_TX
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#define CONFIG_UART_TX_DMA_PH 2
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/* Optional features */
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#define CONFIG_CMD_SPI_XFER
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#define CONFIG_HOST_COMMAND_STATUS
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#undef CONFIG_LID_SWITCH
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#define CONFIG_MKBP_EVENT
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#define CONFIG_FPU
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#define CONFIG_PRINTF_LEGACY_LI_FORMAT
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#define CONFIG_SPI
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#define CONFIG_SPI_MASTER
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#define CONFIG_STM_HWTIMER32
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#define CONFIG_WATCHDOG_HELP
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/* Fingerprint configuration */
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#define CONFIG_SPI_FP_PORT 1 /* SPI3: second SPI master port */
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#define CONFIG_FP_SENSOR_FPC1145
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#define CONFIG_CMD_FPSENSOR_DEBUG
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/* Timer selection */
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#define TIM_CLOCK32 2
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#define TIM_WATCHDOG 16
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/*
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* PLL configuration for 80Mhz:
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* SYSCLK = HSE * n/m/r = 16 * 10 / 2 = 80 Mhz
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*/
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#undef STM32_PLLM
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#define STM32_PLLM 1
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#undef STM32_PLLN
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#define STM32_PLLN 10
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#undef STM32_PLLR
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#define STM32_PLLR 2
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#ifndef __ASSEMBLER__
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#include "gpio_signal.h"
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void fps_event(enum gpio_signal signal);
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#endif /* !__ASSEMBLER__ */
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#endif /* __CROS_EC_BOARD_H */
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@@ -1,12 +0,0 @@
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# Copyright 2017 The Chromium OS Authors. All rights reserved.
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# Use of this source code is governed by a BSD-style license that can be
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# found in the LICENSE file.
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#
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# Board specific files build
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# the IC is STmicroelectronics STM32L442KC
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CHIP:=stm32
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CHIP_FAMILY:=stm32l4
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CHIP_VARIANT:=stm32l442
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board-y=board.o
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@@ -1,24 +0,0 @@
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/* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/**
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* List of enabled tasks in the priority order
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*
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* The first one has the lowest priority.
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*
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* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
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* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
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* where :
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* 'n' in the name of the task
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* 'r' in the main routine of the task
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* 'd' in an opaque parameter passed to the routine at startup
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* 's' is the stack size in bytes; must be a multiple of 8
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*/
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#define CONFIG_TASK_LIST \
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TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
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TASK_ALWAYS(FPSENSOR, fp_task, NULL, 4096) \
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TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
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TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
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@@ -1,28 +0,0 @@
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/*
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* Copyright 2017 The Chromium OS Authors. All rights reserved.
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* Use of this source code is governed by a BSD-style license that can be
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* found in the LICENSE file.
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*/
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/* Declare symbolic names for all the GPIOs that we care about.
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* Note: Those with interrupt handlers must be declared first. */
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GPIO_INT(FPS_INT, PIN(A, 2), GPIO_INT_RISING, fps_event)
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GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INPUT, spi_event)
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GPIO_INT(SLP_S3_L, PIN(A, 11), GPIO_INT_BOTH, slp_event)
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/* Outputs */
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GPIO(EC_INT_L, PIN(A, 1), GPIO_INPUT) /* Enabled when PCH is up */
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GPIO(FP_RST_ODL, PIN(A, 3), GPIO_ODR_LOW)
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GPIO(SPI3_NSS, PIN(A, 15), GPIO_OUT_HIGH)
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GPIO(WP_L, PIN(B, 7), GPIO_INPUT)
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/* Unimplemented signals which we need to emulate */
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UNIMPLEMENTED(ENTERING_RW)
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/* USART1: PA9/10 */
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ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_F7, MODULE_UART, 0)
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/* SPI1 slave from PCH: PA4/5/6/7 */
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ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_F5, MODULE_SPI, 0)
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/* SPI3 master to sensor: PB3/4/5 */
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ALTERNATE(PIN_MASK(B, 0x0038), GPIO_ALT_F6, MODULE_SPI_MASTER, 0)
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@@ -60,7 +60,6 @@ BOARDS_STM32=(
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chell_pd
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coffeecake
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elm
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eve_fp
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glados_pd
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hammer
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jerry
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@@ -453,7 +452,7 @@ function servo_ec_uart() {
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case "${BOARD}" in
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oak_pd|samus_pd|strago_pd ) MCU="usbpd" ;;
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chell_pd|glados_pd ) MCU="usbpd" ;;
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eve_fp|meowth_fp ) MCU="usbpd" ;;
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meowth_fp ) MCU="usbpd" ;;
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dingdong|hoho|twinkie ) DUT_CONTROL_CMD="true" ; MCU="ec" ;;
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*) MCU="ec" ;;
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esac
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