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Create samus board config

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This just does a copy/rename from Bolt. Tweaking for Samus' peculiarities
will come next.

BUG=chrome-os-partner:22870
BRANCH=none
TEST=manual

The only thing we can check is that it compiles:

  cd src/platform/ec
  make BOARD=samus

Change-Id: Ied95ebdd1137548b21334b4a65a298c68482c517
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171081
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Bill Richardson
2013-09-30 09:36:01 -07:00
committed by chrome-internal-fetch
parent 6d522eef9d
commit af34e526db
8 changed files with 917 additions and 2 deletions
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247
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* EC for Samus board configuration */
#include "adc.h"
#include "board.h"
#include "backlight.h"
#include "chip_temp_sensor.h"
#include "chipset_haswell.h"
#include "chipset_x86_common.h"
#include "common.h"
#include "ec_commands.h"
#include "extpower.h"
#include "gpio.h"
#include "host_command.h"
#include "i2c.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "lm4_adc.h"
#include "peci.h"
#include "power_button.h"
#include "pwm.h"
#include "pwm_data.h"
#include "registers.h"
#include "switch.h"
#include "temp_sensor.h"
#include "timer.h"
#include "thermal.h"
#include "tmp006.h"
#include "util.h"
/* GPIO signal list. Must match order from enum gpio_signal. */
const struct gpio_info gpio_list[] = {
/* Inputs with interrupt handlers are first for efficiency */
{"POWER_BUTTON_L", LM4_GPIO_A, (1<<2), GPIO_INT_BOTH,
power_button_interrupt},
{"LID_OPEN", LM4_GPIO_A, (1<<3), GPIO_INT_BOTH,
lid_interrupt},
{"AC_PRESENT", LM4_GPIO_H, (1<<3), GPIO_INT_BOTH,
extpower_interrupt},
{"PCH_BKLTEN", LM4_GPIO_M, (1<<3), GPIO_INT_BOTH,
backlight_interrupt},
{"PCH_SLP_S0_L", LM4_GPIO_G, (1<<6), GPIO_INT_BOTH,
x86_interrupt},
{"PCH_SLP_S3_L", LM4_GPIO_G, (1<<7), GPIO_INT_BOTH,
x86_interrupt},
{"PCH_SLP_S5_L", LM4_GPIO_H, (1<<1), GPIO_INT_BOTH,
x86_interrupt},
{"PCH_SLP_SUS_L", LM4_GPIO_G, (1<<3), GPIO_INT_BOTH,
x86_interrupt},
{"PCH_SUSWARN_L", LM4_GPIO_G, (1<<2), GPIO_INT_BOTH,
x86_interrupt},
/* EC needs to control PP1050_PGOOD as it goes to VCCST_PGOOD. */
{"PP1050_PGOOD", LM4_GPIO_H, (1<<4), GPIO_ODR_LOW, NULL },
{"PP1350_PGOOD", LM4_GPIO_H, (1<<6), GPIO_INT_BOTH,
x86_interrupt},
{"PP5000_PGOOD", LM4_GPIO_N, (1<<0), GPIO_INT_BOTH,
x86_interrupt},
{"VCORE_PGOOD", LM4_GPIO_C, (1<<6), GPIO_INT_BOTH,
x86_interrupt},
{"PCH_EDP_VDD_EN", LM4_GPIO_J, (1<<1), GPIO_INT_BOTH,
haswell_interrupt},
{"RECOVERY_L", LM4_GPIO_A, (1<<5), GPIO_PULL_UP|GPIO_INT_BOTH,
switch_interrupt},
{"WP", LM4_GPIO_A, (1<<4), GPIO_INT_BOTH,
switch_interrupt},
/* Other inputs */
{"BOARD_VERSION1", LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
{"BOARD_VERSION2", LM4_GPIO_Q, (1<<6), GPIO_INPUT, NULL},
{"BOARD_VERSION3", LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
{"CPU_PGOOD", LM4_GPIO_C, (1<<4), GPIO_INPUT, NULL},
{"ONEWIRE", LM4_GPIO_F, (1<<7), GPIO_INPUT, NULL},
{"PCH_CATERR_L", LM4_GPIO_F, (1<<3), GPIO_INPUT, NULL},
{"THERMAL_DATA_READY_L", LM4_GPIO_B, (1<<0), GPIO_INPUT, NULL},
{"USB1_OC_L", LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
{"USB1_STATUS_L", LM4_GPIO_E, (1<<6), GPIO_INPUT, NULL},
{"USB2_OC_L", LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},
{"USB2_STATUS_L", LM4_GPIO_D, (1<<7), GPIO_INPUT, NULL},
/* Outputs; all unasserted by default except for reset signals */
{"CPU_PROCHOT", LM4_GPIO_B, (1<<1), GPIO_OUT_LOW, NULL},
{"PP1350_EN", LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
{"PP3300_DSW_GATED_EN", LM4_GPIO_J, (1<<3), GPIO_OUT_LOW, NULL},
{"PP3300_DX_EN", LM4_GPIO_F, (1<<6), GPIO_OUT_LOW, NULL},
{"PP3300_LTE_EN", LM4_GPIO_D, (1<<2), GPIO_OUT_LOW, NULL},
{"PP3300_WLAN_EN", LM4_GPIO_J, (1<<0), GPIO_OUT_LOW, NULL},
{"PP1050_EN", LM4_GPIO_C, (1<<7), GPIO_OUT_LOW, NULL},
{"VCORE_EN", LM4_GPIO_C, (1<<5), GPIO_OUT_LOW, NULL},
{"PP5000_EN", LM4_GPIO_H, (1<<7), GPIO_OUT_LOW, NULL},
{"SYS_PWROK", LM4_GPIO_H, (1<<2), GPIO_OUT_LOW, NULL},
{"WLAN_OFF_L", LM4_GPIO_J, (1<<4), GPIO_OUT_LOW, NULL},
{"ENABLE_BACKLIGHT", LM4_GPIO_M, (1<<7), GPIO_OUT_LOW, NULL},
{"ENABLE_TOUCHPAD", LM4_GPIO_N, (1<<1), GPIO_OUT_LOW, NULL},
{"ENTERING_RW", LM4_GPIO_D, (1<<3), GPIO_OUT_LOW, NULL},
{"LIGHTBAR_RESET_L", LM4_GPIO_J, (1<<2), GPIO_OUT_LOW, NULL},
{"PCH_DPWROK", LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL},
/*
* HDA_SDO is technically an output, but we need to leave it as an
* input until we drive it high. So can't use open-drain (HI_Z).
*/
{"PCH_HDA_SDO", LM4_GPIO_G, (1<<1), GPIO_INPUT, NULL},
{"PCH_WAKE_L", LM4_GPIO_F, (1<<0), GPIO_OUT_HIGH, NULL},
{"PCH_NMI_L", LM4_GPIO_F, (1<<2), GPIO_ODR_HIGH, NULL},
{"PCH_PWRBTN_L", LM4_GPIO_H, (1<<0), GPIO_OUT_HIGH, NULL},
{"PCH_PWROK", LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
/* FIXME: Why is PL6 act like it is inverted. Setting value to
* 0 makes the signal high, and setting it to 1 makes the signal low. */
{"PCH_RCIN_L", LM4_GPIO_L, (1<<6), GPIO_INPUT, NULL},
{"PCH_SYSRST_L", LM4_GPIO_F, (1<<1), GPIO_ODR_HIGH, NULL},
{"PCH_SMI_L", LM4_GPIO_F, (1<<4), GPIO_ODR_HIGH, NULL},
{"TOUCHSCREEN_RESET_L", LM4_GPIO_N, (1<<7), GPIO_OUT_LOW, NULL},
{"EC_EDP_VDD_EN", LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL},
{"LPC_CLKRUN_L", LM4_GPIO_M, (1<<2), GPIO_ODR_HIGH, NULL},
{"USB1_CTL1", LM4_GPIO_E, (1<<1), GPIO_OUT_LOW, NULL},
{"USB1_CTL2", LM4_GPIO_E, (1<<2), GPIO_OUT_HIGH, NULL},
{"USB1_CTL3", LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL},
{"USB1_ENABLE", LM4_GPIO_E, (1<<4), GPIO_OUT_HIGH, NULL},
{"USB1_ILIM_SEL", LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL},
{"USB2_CTL1", LM4_GPIO_D, (1<<0), GPIO_OUT_LOW, NULL},
{"USB2_CTL2", LM4_GPIO_D, (1<<1), GPIO_OUT_HIGH, NULL},
{"USB2_CTL3", LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL},
{"USB2_ENABLE", LM4_GPIO_D, (1<<5), GPIO_OUT_HIGH, NULL},
{"USB2_ILIM_SEL", LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
};
BUILD_ASSERT(ARRAY_SIZE(gpio_list) == GPIO_COUNT);
/* Pins with alternate functions */
const struct gpio_alt_func gpio_alt_funcs[] = {
{GPIO_A, 0x03, 1, MODULE_UART}, /* UART0 */
{GPIO_A, 0x40, 3, MODULE_I2C}, /* I2C1 SCL */
{GPIO_A, 0x80, 3, MODULE_I2C, GPIO_OPEN_DRAIN}, /* I2C1 SDA */
{GPIO_B, 0x04, 3, MODULE_I2C}, /* I2C0 SCL */
{GPIO_B, 0x08, 3, MODULE_I2C, GPIO_OPEN_DRAIN}, /* I2C0 SDA */
{GPIO_B, 0x40, 3, MODULE_I2C}, /* I2C5 SCL */
{GPIO_B, 0x80, 3, MODULE_I2C, GPIO_OPEN_DRAIN}, /* I2C5 SDA */
{GPIO_G, 0x30, 1, MODULE_UART}, /* UART2 */
{GPIO_J, 0x40, 1, MODULE_PECI}, /* PECI Tx */
{GPIO_J, 0x80, 0, MODULE_PECI, GPIO_ANALOG}, /* PECI Rx */
{GPIO_L, 0x3f, 15, MODULE_LPC}, /* LPC */
{GPIO_M, 0x33, 15, MODULE_LPC}, /* LPC */
{GPIO_N, 0x0c, 1, MODULE_PWM_FAN}, /* Fan0 PWM/tach */
{GPIO_N, 0x40, 1, MODULE_PWM_KBLIGHT}, /* Fan1 PWM */
};
const int gpio_alt_funcs_count = ARRAY_SIZE(gpio_alt_funcs);
/* x86 signal list. Must match order of enum x86_signal. */
const struct x86_signal_info x86_signal_list[] = {
{GPIO_PP5000_PGOOD, 1, "PGOOD_PP5000"},
{GPIO_PP1350_PGOOD, 1, "PGOOD_PP1350"},
{GPIO_VCORE_PGOOD, 1, "PGOOD_VCORE"},
{GPIO_PCH_SLP_S0_L, 1, "SLP_S0#_DEASSERTED"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3#_DEASSERTED"},
{GPIO_PCH_SLP_S5_L, 1, "SLP_S5#_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(x86_signal_list) == X86_SIGNAL_COUNT);
/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
const struct adc_t adc_channels[] = {
/* EC internal temperature is calculated by
* 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
* = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
*/
{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
/* IOUT == ICMNT is on PE3/AIN0 */
/* We have 0.01-ohm resistors, and IOUT is 20X the differential
* voltage, so 1000mA ==> 200mV.
* ADC returns 0x000-0xFFF, which maps to 0.0-3.3V (as configured).
* mA = 1000 * ADC_VALUE / ADC_READ_MAX * 3300 / 200
*/
{"ChargerCurrent", LM4_ADC_SEQ1, 33000, ADC_READ_MAX * 2, 0,
LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* PWM channels */
const struct pwm_t pwm_channels[] = {
[PWM_CH_FAN] = {CONFIG_FAN_CH_CPU, PWM_CONFIG_HAS_RPM_MODE},
[PWM_CH_KBLIGHT] = {4, 0},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
/* Note: battery and charger share a port. Only include it once in
* this list so we don't double-initialize it. */
{"batt_chg", I2C_PORT_BATTERY, 100},
{"lightbar", I2C_PORT_LIGHTBAR, 400},
{"thermal", I2C_PORT_THERMAL, 100},
};
BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_PORTS_USED);
/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
const struct temp_sensor_t temp_sensors[] = {
/* HEY: Need correct I2C addresses and read function for external sensor */
{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0, 2},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
{ {0, 0, 0}, 0, 0},
/* Only the AP affects the thermal limits and fan speed. */
{{C_TO_K(100), C_TO_K(114), C_TO_K(110)}, C_TO_K(60), C_TO_K(90)},
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
struct keyboard_scan_config keyscan_config = {
.output_settle_us = 40,
.debounce_down_us = 6 * MSEC,
.debounce_up_us = 30 * MSEC,
.scan_period_us = 1500,
.min_post_scan_delay_us = 1000,
.poll_timeout_us = SECOND,
.actual_key_mask = {
0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8 /* full set */
},
};
/**
* Perform necessary actions on host wake events.
*/
void board_process_wake_events(uint32_t active_wake_events)
{
uint32_t power_button_mask;
power_button_mask = EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON);
/* If there are other events aside from the power button press drive
* the wake pin. Otherwise ensure it is high. */
if (active_wake_events & ~power_button_mask)
gpio_set_level(GPIO_PCH_WAKE_L, 0);
else
gpio_set_level(GPIO_PCH_WAKE_L, 1);
}

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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Configuration for Samus mainboard */
#ifndef __BOARD_H
#define __BOARD_H
/* Debug features */
#define CONFIG_ASSERT_HELP
#define CONFIG_CONSOLE_CMDHELP
#define CONFIG_PANIC_HELP
#define CONFIG_TASK_PROFILING
/* Optional features */
#define CONFIG_CHIPSET_X86
#define CONFIG_CHIPSET_CAN_THROTTLE
#define CONFIG_CUSTOM_KEYSCAN
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_KEYBOARD_BOARD_CONFIG
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_DRIVER_DS2413
#define CONFIG_ONEWIRE
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_WP_ACTIVE_HIGH
#define CONFIG_BATTERY_LINK
#define CONFIG_BATTERY_SMART
#define CONFIG_BACKLIGHT_LID
#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
#define CONFIG_CHARGER
#define CONFIG_CHARGER_BQ24715
/* 10mOhm sense resitors. */
#define CONFIG_CHARGER_SENSE_RESISTOR 10
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10
/* External Charger maximum current. */
#define CONFIG_CHARGER_INPUT_CURRENT 5000
#define CONFIG_FAN
#define CONFIG_FAN_CH_CPU 2
#define CONFIG_FAN_RPM_MIN 1000
#define CONFIG_FAN_RPM_MAX 5050
#define CONFIG_FAN_POWER_GOOD GPIO_PP5000_PGOOD
#define CONFIG_PWM
#define CONFIG_PWM_KBLIGHT
#define CONFIG_SWITCH_DEDICATED_RECOVERY
#define CONFIG_TEMP_SENSOR
#define CONFIG_UART_HOST 2
#define CONFIG_WIRELESS
#if 0
#define CONFIG_USB_PORT_POWER_DUMB
#endif
#ifndef __ASSEMBLER__
/* Module IDs */
/* TODO(rspangler): use this in place of enum console_channel as well */
enum module_id {
MODULE_I2C,
MODULE_LPC,
MODULE_PECI,
MODULE_PWM_FAN,
MODULE_PWM_KBLIGHT,
MODULE_UART,
};
/* I2C ports */
#define I2C_PORT_BATTERY 0
#define I2C_PORT_CHARGER 0
#define I2C_PORT_LIGHTBAR 1
#define I2C_PORT_THERMAL 5
/* There are only 3 I2C ports used because battery and charger share a port */
#define I2C_PORTS_USED 3
/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
#define KB_SCAN_ROW_IRQ LM4_IRQ_GPIOK
#define KB_SCAN_ROW_GPIO LM4_GPIO_K
/* Host connects to keyboard controller module via LPC */
#define HOST_KB_BUS_LPC
/* USB ports */
#define USB_PORT_COUNT 2
/* GPIO signal definitions. */
enum gpio_signal {
/* Inputs with interrupt handlers are first for efficiency */
GPIO_POWER_BUTTON_L = 0, /* Power button */
GPIO_LID_OPEN, /* Lid switch */
GPIO_AC_PRESENT, /* AC power present */
GPIO_PCH_BKLTEN, /* Backlight enable signal from PCH */
GPIO_PCH_SLP_S0_L, /* SLP_S0# signal from PCH */
GPIO_PCH_SLP_S3_L, /* SLP_S3# signal from PCH */
GPIO_PCH_SLP_S5_L, /* SLP_S5# signal from PCH */
GPIO_PCH_SLP_SUS_L, /* SLP_SUS# signal from PCH */
GPIO_PCH_SUSWARN_L, /* SUSWARN# signal from PCH */
GPIO_PP1050_PGOOD, /* Power good on 1.05V */
GPIO_PP1350_PGOOD, /* Power good on 1.35V (DRAM) */
GPIO_PP5000_PGOOD, /* Power good on 5V */
GPIO_VCORE_PGOOD, /* Power good on core VR */
GPIO_PCH_EDP_VDD_EN, /* PCH wants EDP enabled */
GPIO_RECOVERY_L, /* Recovery signal from servo */
GPIO_WP, /* Write protect input */
/* Other inputs */
GPIO_BOARD_VERSION1, /* Board version stuffing resistor 1 */
GPIO_BOARD_VERSION2, /* Board version stuffing resistor 2 */
GPIO_BOARD_VERSION3, /* Board version stuffing resistor 3 */
GPIO_CPU_PGOOD, /* Power good to the CPU */
GPIO_ONEWIRE, /* One-wire bus to adapter LED */
GPIO_PCH_CATERR_L, /* Catastrophic error signal from PCH */
GPIO_THERMAL_DATA_READY_L, /* From thermal sensor */
GPIO_USB1_OC_L, /* USB port overcurrent warning */
GPIO_USB1_STATUS_L, /* USB charger port 1 status output */
GPIO_USB2_OC_L, /* USB port overcurrent warning */
GPIO_USB2_STATUS_L, /* USB charger port 2 status output */
/* Outputs */
GPIO_CPU_PROCHOT, /* Force CPU to think it's overheated */
GPIO_PP1350_EN, /* Enable 1.35V supply */
GPIO_PP3300_DSW_GATED_EN, /* Enable DSW rails */
GPIO_PP3300_DX_EN, /* Enable power to lots of peripherals */
GPIO_PP3300_LTE_EN, /* Enable LTE radio */
GPIO_PP3300_WLAN_EN, /* Enable WiFi power */
GPIO_PP1050_EN, /* Enable 1.05V regulator */
GPIO_VCORE_EN, /* Stuffing option - not connected */
GPIO_PP5000_EN, /* Enable 5V supply */
GPIO_SYS_PWROK, /* EC thinks everything is up and ready */
GPIO_WLAN_OFF_L, /* Disable WiFi radio */
GPIO_ENABLE_BACKLIGHT, /* Enable backlight power */
GPIO_ENABLE_TOUCHPAD, /* Enable touchpad power */
GPIO_ENTERING_RW, /* Indicate when EC is entering RW code */
GPIO_LIGHTBAR_RESET_L, /* Reset lightbar controllers */
GPIO_PCH_DPWROK, /* Indicate when VccDSW is good */
GPIO_PCH_HDA_SDO, /* HDA_SDO signal to PCH; when high, ME
* ignores security descriptor */
GPIO_PCH_WAKE_L, /* Wake signal from EC to PCH */
GPIO_PCH_NMI_L, /* Non-maskable interrupt pin to PCH */
GPIO_PCH_PWRBTN_L, /* Power button output to PCH */
GPIO_PCH_PWROK, /* PWROK / APWROK signals to PCH */
GPIO_PCH_RCIN_L, /* RCIN# line to PCH (for 8042 emulation) */
GPIO_PCH_SYS_RST_L, /* Reset PCH resume power plane logic */
GPIO_PCH_SMI_L, /* System management interrupt to PCH */
GPIO_TOUCHSCREEN_RESET_L, /* Reset touch screen */
GPIO_EC_EDP_VDD_EN, /* Enable EDP (passthru from PCH) */
GPIO_LPC_CLKRUN_L, /* Dunno. Probably important, though. */
GPIO_USB1_CTL1, /* USB charger port 1 CTL1 output */
GPIO_USB1_CTL2, /* USB charger port 1 CTL2 output */
GPIO_USB1_CTL3, /* USB charger port 1 CTL3 output */
GPIO_USB1_ENABLE, /* USB charger port 1 enable */
GPIO_USB1_ILIM_SEL, /* USB charger port 1 ILIM_SEL output */
GPIO_USB2_CTL1, /* USB charger port 2 CTL1 output */
GPIO_USB2_CTL2, /* USB charger port 2 CTL2 output */
GPIO_USB2_CTL3, /* USB charger port 2 CTL3 output */
GPIO_USB2_ENABLE, /* USB charger port 2 enable */
GPIO_USB2_ILIM_SEL, /* USB charger port 2 ILIM_SEL output */
/* Number of GPIOs; not an actual GPIO */
GPIO_COUNT
};
/* x86 signal definitions */
enum x86_signal {
X86_PGOOD_PP5000 = 0,
X86_PGOOD_PP1350,
X86_PGOOD_VCORE,
X86_PCH_SLP_S0n_DEASSERTED,
X86_PCH_SLP_S3n_DEASSERTED,
X86_PCH_SLP_S5n_DEASSERTED,
X86_PCH_SLP_SUSn_DEASSERTED,
/* Number of X86 signals */
X86_SIGNAL_COUNT
};
enum adc_channel {
/* EC internal die temperature in degrees K. */
ADC_CH_EC_TEMP = 0,
/* Charger current in mA. */
ADC_CH_CHARGER_CURRENT,
ADC_CH_COUNT
};
enum pwm_channel {
PWM_CH_FAN,
PWM_CH_KBLIGHT,
/* Number of PWM channels */
PWM_CH_COUNT
};
enum temp_sensor_id {
/* HEY - need two I2C sensor values, and put PECI first */
/* EC internal temperature sensor */
TEMP_SENSOR_EC_INTERNAL,
/* CPU die temperature via PECI */
TEMP_SENSOR_CPU_PECI,
TEMP_SENSOR_COUNT
};
/* Known board versions for system_get_board_version(). */
enum board_version {
BOARD_VERSION_PROTO1 = 0,
BOARD_VERSION_EVT = 1,
};
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

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# -*- makefile -*-
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is TI Stellaris LM4
CHIP:=lm4
board-y=board.o power_sequence.o

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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' is the name of the task
* 'r' is the main routine of the task
* 'd' is an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(VBOOTHASH, vboot_hash_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

390
board/samus/power_sequence.c Normal file
View File

@@ -0,0 +1,390 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* X86 chipset power control module for Chrome EC */
#include "chipset.h"
#include "chipset_x86_common.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "lid_switch.h"
#include "registers.h"
#include "system.h"
#include "timer.h"
#include "util.h"
#include "wireless.h"
/* Console output macros */
#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
#define CPRINTF(format, args...) cprintf(CC_CHIPSET, format, ## args)
/* Input state flags */
#define IN_PGOOD_PP5000 X86_SIGNAL_MASK(X86_PGOOD_PP5000)
#define IN_PGOOD_PP1350 X86_SIGNAL_MASK(X86_PGOOD_PP1350)
#define IN_PGOOD_VCORE X86_SIGNAL_MASK(X86_PGOOD_VCORE)
#define IN_PCH_SLP_S0n_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_S0n_DEASSERTED)
#define IN_PCH_SLP_S3n_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_S3n_DEASSERTED)
#define IN_PCH_SLP_S5n_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_S5n_DEASSERTED)
#define IN_PCH_SLP_SUSn_DEASSERTED X86_SIGNAL_MASK(X86_PCH_SLP_SUSn_DEASSERTED)
/* All always-on supplies */
#define IN_PGOOD_ALWAYS_ON (IN_PGOOD_PP5000)
/* All non-core power rails */
#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1350)
/* All core power rails */
#define IN_PGOOD_ALL_CORE (IN_PGOOD_VCORE)
/* Rails required for S3 */
#define IN_PGOOD_S3 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_PP1350)
/* Rails required for S0 */
#define IN_PGOOD_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
/* All PM_SLP signals from PCH deasserted */
#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3n_DEASSERTED | \
IN_PCH_SLP_S5n_DEASSERTED)
/* All inputs in the right state for S0 */
#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE | \
IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
static int throttle_cpu; /* Throttle CPU? */
void chipset_force_shutdown(void)
{
CPRINTF("[%T %s()]\n", __func__);
/*
* Force x86 off. This condition will reset once the state machine
* transitions to G3.
*/
gpio_set_level(GPIO_PCH_DPWROK, 0);
}
void chipset_reset(int cold_reset)
{
CPRINTF("[%T %s(%d)]\n", __func__, cold_reset);
if (cold_reset) {
/*
* Drop and restore PWROK. This causes the PCH to reboot,
* regardless of its after-G3 setting. This type of reboot
* causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
* we actually drop power to the rest of the system (hence, a
* "cold" reboot).
*/
/* Ignore if PWROK is already low */
if (gpio_get_level(GPIO_PCH_PWROK) == 0)
return;
/* PWROK must deassert for at least 3 RTC clocks = 91 us */
gpio_set_level(GPIO_PCH_PWROK, 0);
udelay(100);
gpio_set_level(GPIO_PCH_PWROK, 1);
} else {
/*
* Send a RCIN# pulse to the PCH. This just causes it to
* assert INIT# to the CPU without dropping power or asserting
* PLTRST# to reset the rest of the system.
*/
/*
* Pulse must be at least 16 PCI clocks long = 500 ns. The gpio
* pin used by the EC (PL6) does not behave in the correct
* manner when configured as open drain. In order to mimic
* open drain, the pin is initially configured as an input.
* When it is needed to drive low, the flags are updated which
* changes the pin to an output and drives the pin low. */
gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_LOW);
udelay(10);
gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_INPUT);
}
}
void chipset_throttle_cpu(int throttle)
{
/* FIXME CPRINTF("[%T %s(%d)]\n", __func__, throttle);*/
}
enum x86_state x86_chipset_init(void)
{
/* Enable interrupts for our GPIOs */
gpio_enable_interrupt(GPIO_PCH_EDP_VDD_EN);
/*
* If we're switching between images without rebooting, see if the x86
* is already powered on; if so, leave it there instead of cycling
* through G3.
*/
if (system_jumped_to_this_image()) {
if ((x86_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
CPRINTF("[%T x86 already in S0]\n");
return X86_S0;
} else {
/* Force all signals to their G3 states */
CPRINTF("[%T x86 forcing G3]\n");
gpio_set_level(GPIO_PCH_PWROK, 0);
gpio_set_level(GPIO_SYS_PWROK, 0);
gpio_set_level(GPIO_VCORE_EN, 0);
gpio_set_level(GPIO_PP1050_EN, 0);
gpio_set_level(GPIO_PP1350_EN, 0);
gpio_set_level(GPIO_PP1050_PGOOD, 0);
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
gpio_set_level(GPIO_PCH_DPWROK, 0);
wireless_enable(0);
}
}
return X86_G3;
}
enum x86_state x86_handle_state(enum x86_state state)
{
switch (state) {
case X86_G3:
break;
case X86_S5:
if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1)
return X86_S5S3; /* Power up to next state */
break;
case X86_S3:
/*
* If lid is closed; hold touchscreen in reset to cut
* power usage. If lid is open, take touchscreen out
* of reset so it can wake the processor.
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
/* Check for state transitions */
if (!x86_has_signals(IN_PGOOD_S3)) {
/* Required rail went away */
chipset_force_shutdown();
return X86_S3S5;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
/* Power up to next state */
return X86_S3S0;
} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
/* Power down to next state */
return X86_S3S5;
}
break;
case X86_S0:
if (!x86_has_signals(IN_PGOOD_S0)) {
/* Required rail went away */
chipset_force_shutdown();
return X86_S0S3;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
/* Power down to next state */
return X86_S0S3;
}
break;
case X86_G3S5:
/*
* Wait 10ms after +3VALW good, since that powers VccDSW and
* VccSUS.
*/
msleep(10);
/* Enable PP5000 (5V) rail as 1.05V and 1.35V rails need 5V
* rail to regulate properly. */
gpio_set_level(GPIO_PP5000_EN, 1);
if (x86_wait_signals(IN_PGOOD_PP5000)) {
chipset_force_shutdown();
return X86_G3;
}
/* Assert DPWROK */
gpio_set_level(GPIO_PCH_DPWROK, 1);
/* Enable PP1050 rail. Bring up the PP1050_PCH_SUS rail to
* provide 1.05V suspend as early as possible as the RSMSRT#
* signal deasserting indicates both the PP3300_PCH_SUS
* and PP1050_PCH_SUS rails are good. Since PP1050_PGGOOD is
* driven as output to work around VCCST_PWRGD timing problems
* there is no way to know when PP1050_PCH_SUS rail is good.
* Similarly the PP3300_PCH_SUS rail is enabled by SLP_SUS#
* being deasserted without a power good signal. The RSMRST#
* is driven by an RC circuit feeding into schmitt trigger.
* Therefore, the PP1050_PCH_SUS rail is brought up as early
* as possible after DPWROK is asserted so that it will be
* ready by the time RSMRST# is deasserted. */
gpio_set_level(GPIO_PP1050_EN, 1);
/* Wait for SLP_SUS# to deassert before enabling PP1050. */
if (x86_wait_signals(IN_PCH_SLP_SUSn_DEASSERTED)) {
chipset_force_shutdown();
return X86_G3;
}
/* Wait 5ms for SUSCLK to stabilize */
msleep(5);
return X86_S5;
case X86_S5S3:
/* Wait for the always-on rails to be good */
if (x86_wait_signals(IN_PGOOD_ALWAYS_ON)) {
chipset_force_shutdown();
return X86_S5;
}
/* Turn on power to RAM */
gpio_set_level(GPIO_PP1350_EN, 1);
if (x86_wait_signals(IN_PGOOD_S3)) {
chipset_force_shutdown();
return X86_S5;
}
/*
* Take lightbar out of reset, now that +5VALW is
* available and we won't leak +3VALW through the reset
* line.
*/
gpio_set_level(GPIO_LIGHTBAR_RESET_L, 1);
/*
* Enable touchpad power so it can wake the system from
* suspend.
*/
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_STARTUP);
return X86_S3;
case X86_S3S0:
/* Wait 20ms before allowing VCCST_PGOOD to rise. */
msleep(20);
/* Assert VCCST_PGOOD using PP1050_PGOOD. */
gpio_set_level(GPIO_PP1050_PGOOD, 1);
/* Turn on power rails */
gpio_set_level(GPIO_PP3300_DX_EN, 1);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 1);
/* Enable wireless */
wireless_enable(EC_WIRELESS_SWITCH_ALL);
/*
* Make sure touchscreen is out if reset (even if the
* lid is still closed); it may have been turned off if
* the lid was closed in S3.
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
/* Wait for non-core power rails good */
if (x86_wait_signals(IN_PGOOD_S0)) {
chipset_force_shutdown();
wireless_enable(0);
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
gpio_set_level(GPIO_PP1050_PGOOD, 0);
return X86_S3;
}
/*
* Enable +CPU_CORE. The CPU itself will request the supplies
* when it's ready.
*/
gpio_set_level(GPIO_VCORE_EN, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_RESUME);
/* Wait 99ms after all voltages good */
msleep(99);
/*
* Throttle CPU if necessary. This should only be asserted
* when +VCCP is powered (it is by now).
*/
gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
/* Set PCH_PWROK */
gpio_set_level(GPIO_PCH_PWROK, 1);
gpio_set_level(GPIO_SYS_PWROK, 1);
return X86_S0;
case X86_S0S3:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SUSPEND);
/* Drop VCCST_PGOOD */
gpio_set_level(GPIO_PP1050_PGOOD, 0);
/* Clear PCH_PWROK */
gpio_set_level(GPIO_SYS_PWROK, 0);
gpio_set_level(GPIO_PCH_PWROK, 0);
/* Wait 40ns */
udelay(1);
/* Disable +CPU_CORE */
gpio_set_level(GPIO_VCORE_EN, 0);
/* Disable wireless */
wireless_enable(0);
/*
* Deassert prochot since CPU is off and we're about to drop
* +VCCP.
*/
gpio_set_level(GPIO_CPU_PROCHOT, 0);
/* Turn off power rails */
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
return X86_S3;
case X86_S3S5:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SHUTDOWN);
/* Disable touchpad power */
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
/* Turn off power to RAM */
gpio_set_level(GPIO_PP1350_EN, 0);
/*
* Put touchscreen and lightbar in reset, so we won't
* leak +3VALW through the reset line to chips powered
* by +5VALW.
*
* (Note that we're no longer powering down +5VALW due
* to crosbug.com/p/16600, but to minimize side effects
* of that change we'll still reset these components in
* S5.)
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
gpio_set_level(GPIO_LIGHTBAR_RESET_L, 0);
return X86_S5;
case X86_S5G3:
/* Deassert DPWROK */
gpio_set_level(GPIO_PCH_DPWROK, 0);
gpio_set_level(GPIO_PP1050_EN, 0);
/* Disable PP5000 (5V) rail. */
gpio_set_level(GPIO_PP5000_EN, 0);
return X86_G3;
}
return state;
}
void haswell_interrupt(enum gpio_signal signal)
{
/* Pass through eDP VDD enable from PCH */
gpio_set_level(GPIO_EC_EDP_VDD_EN, gpio_get_level(GPIO_PCH_EDP_VDD_EN));
}

14
chip/lm4/openocd/lm4x_cmds.tcl
View File

@@ -39,7 +39,19 @@ proc flash_rambi { } {
flash_lm4 ../../../build/rambi/ec.bin 0
}
# Bolt/slippy/falco/peppy have 128KB images
# 128KB images
proc flash_samus { } {
flash_lm4 ../../../build/samus/ec.bin 0
}
proc flash_samus_ro { } {
flash_lm4 ../../../build/samus/ec.RO.flat 0
}
proc flash_samus_rw { } {
flash_lm4 ../../../build/samus/ec.RW.bin 131072
}
proc flash_bolt { } {
flash_lm4 ../../../build/bolt/ec.bin 0
}

1
test/build.mk
View File

@@ -25,6 +25,7 @@ test-list-$(BOARD_slippy)=
test-list-$(BOARD_falco)=
test-list-$(BOARD_peppy)=
test-list-$(BOARD_bolt)=
test-list-$(BOARD_samus)=
# Emulator tests
test-list-host=mutex pingpong utils kb_scan kb_mkbp lid_sw power_button hooks

2
util/flash_ec
View File

@@ -223,7 +223,7 @@ save="$(servo_save)"
case "${BOARD}" in
daisy | kirby | pit | puppy | snow | spring | discovery ) flash_stm32 ;;
bolt | falco | peppy | rambi | slippy ) flash_lm4 ;;
bolt | samus | falco | peppy | rambi | slippy ) flash_lm4 ;;
link ) flash_link ;;
*) die "board ${BOARD} not supported" ;;
esac