scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-15 00:56:22 +00:00
Code Issues Packages Projects Releases Wiki Activity

oak: revise warm reset control for rev3

Browse Source 
The AP warm reset pin is changed from rev3 of oak board.
PB3 is stuffed before rev3 and connected to PMIC RESET pin to
reset the AP. For rev3, the AP reset mechanism is changed:
PC3 connects to PMIC SYSRSTB, pull PC3 to low, to reset AP.

BRANCH=none
BUG=none
TEST=manual
1. define CONFIG_BOARD_OAK_REV_2 in board.h
   make -j BOARD=oak
2. define CONFIG_BOARD_OAK_REV_3 in board.h
   make -j BOARD=oak
both cases should be built successfully and run "apreset" command.
AP should be reset normally.

Change-Id: I979e93acf755509f8cb7a12dd77eb7c9e7a98ccc
Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/289476
Reviewed-by: Rong Chang <rongchang@chromium.org>
This commit is contained in:
Ben Lok
2015-07-31 17:19:36 +08:00
committed by ChromeOS Commit Bot
parent 70858deabc
commit b147dd7fa6
1 changed files with 21 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
power/mediatek.c
View File

@@ -265,15 +265,27 @@ static void set_pmic_pwron(int asserted)
}
/**
* Set the PMIC WARM RESET signal.
* Set the WARM RESET signal.
*
* @param asserted Resetting (=0) or idle (=1)
* PMIC_WARM_RESET_H (PB3) is stuffed before rev < 3 and connected to PMIC RESET
* After rev >= 3, this is removed. This should not effected the new board.
*
* AP_RESET_L (PC3, CPU_WARM_RESET_L) is stuffed after rev >= 3
* and connected to PMIC SYSRSTB
*
* @param asserted off (=0) or on (=1)
*/
static void set_pmic_warm_reset(int asserted)
static void set_warm_reset(int asserted)
{
/* Signal is active-high */
/* @param asserted: Resetting (=0) or idle (=1) */
gpio_set_level(GPIO_PMIC_WARM_RESET_H, asserted);
if (system_get_board_version() < 3) {
/* Signal is active-high */
CPRINTS("pmic warm reset(%d)", asserted);
gpio_set_level(GPIO_PMIC_WARM_RESET_H, asserted);
} else {
/* Signal is active-low */
CPRINTS("ap warm reset(%d)", asserted);
gpio_set_level(GPIO_AP_RESET_L, !asserted);
}
}
/**
@@ -565,7 +577,7 @@ static void power_on(void)
GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH);
/* Make sure we de-assert and GPIO_PMIC_WARM_RESET_H pin. */
set_pmic_warm_reset(0);
set_warm_reset(0);
/*
* Before we push PMIC power button, wait for the PMI RTC ready, which
@@ -646,10 +658,10 @@ void chipset_reset(int is_cold)
set_pmic_pwron(0);
} else {
CPRINTS("EC triggered warm reboot");
set_pmic_warm_reset(1);
set_warm_reset(1);
usleep(PMIC_WARM_RESET_H_HOLD_TIME);
/* deassert the reset signals */
set_pmic_warm_reset(0);
set_warm_reset(0);
}
}