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mec1322: Use internal SCI pin control

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Instead of requiring a GPIO definition, default to using the internal
SCI pin control.

BUG=chrome-os-partner:24550
TEST=Trigger SCI and verify with logic analyzer
BRANCH=None

Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182010
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Vic (Chun-Ju) Yang
2014-01-09 11:53:17 +08:00
committed by chrome-internal-fetch
parent 72481572aa
commit b6f8f36aa4
4 changed files with 23 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/mec1322_evb/board.c
View File

@@ -21,7 +21,6 @@ const struct gpio_info gpio_list[] = {
{"LED2", GPIO_PORT(15), (1 << 5), GPIO_ODR_HIGH, NULL},
{"LED3", GPIO_PORT(15), (1 << 6), GPIO_ODR_LOW, NULL},
{"PCH_SMI_L", GPIO_PORT(4), (1 << 4), GPIO_ODR_HIGH, NULL},
{"PCH_SCI_L", GPIO_PORT(2), (1 << 6), GPIO_ODR_HIGH, NULL},
{"PCH_WAKE_L", GPIO_PORT(20), (1 << 0), GPIO_ODR_HIGH, NULL},
/* Unimplemented signals which we need to emulate for now */
GPIO_SIGNAL_NOT_IMPLEMENTED("RECOVERY_L"),
@@ -47,6 +46,7 @@ const struct gpio_alt_func gpio_alt_funcs[] = {
{GPIO_PORT(10), 0xd8, 3, MODULE_KEYBOARD_SCAN, GPIO_KB_OUTPUT},
{GPIO_PORT(12), 0x60, 2, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT},
{GPIO_PORT(14), 0x14, 3, MODULE_KEYBOARD_SCAN, GPIO_KB_INPUT},
{GPIO_PORT(2), 0x20, 2, MODULE_LPC},
};
const int gpio_alt_funcs_count = ARRAY_SIZE(gpio_alt_funcs);

1
board/mec1322_evb/board.h
View File

@@ -39,7 +39,6 @@ enum gpio_signal {
GPIO_LED2,
GPIO_LED3,
GPIO_PCH_SMI_L, /* SMI output */
GPIO_PCH_SCI_L, /* SCI output */
GPIO_PCH_WAKE_L, /* PCH wake pin */
/*
* Signals which aren't implemented on MEC1322 eval board but we'll

13
chip/mec1322/lpc.c
View File

@@ -48,10 +48,15 @@ static void lpc_generate_smi(void)
static void lpc_generate_sci(void)
{
/* TODO (crosbug.com/p/24550): Use EC_SCI# instead of GPIO */
gpio_set_level(GPIO_PCH_SCI_L, 0);
#ifdef CONFIG_SCI_GPIO
gpio_set_level(CONFIG_SCI_GPIO, 0);
udelay(65);
gpio_set_level(GPIO_PCH_SCI_L, 1);
gpio_set_level(CONFIG_SCI_GPIO, 1);
#else
MEC1322_ACPI_PM_STS |= 1;
udelay(65);
MEC1322_ACPI_PM_STS &= ~1;
#endif
}
/**
@@ -158,6 +163,8 @@ static void setup_lpc(void)
if (ptr < 0x120000)
ptr = ptr - 0x118000 + 0x20000000;
gpio_config_module(MODULE_LPC, 1);
/* Set up ACPI0 for 0x62/0x66 */
MEC1322_LPC_ACPI_EC0_BAR = 0x00628034;
MEC1322_INT_ENABLE(15) |= 1 << 6;

12
chip/mec1322/registers.h
View File

@@ -190,6 +190,18 @@ static inline uintptr_t gpio_port_base(int port_id)
#define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105)
#define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y))
#define MEC1322_ACPI_PM_RT_BASE 0x400f1400
#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0)
#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1)
#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2)
#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3)
#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4)
#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5)
#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6)
#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7)
#define MEC1322_ACPI_PM_EC_BASE 0x400f1500
#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10)
/* 8042 */
#define MEC1322_8042_BASE 0x400f0400