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chell: Enable S0ix power state support

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Enable the config option for S0IX power control and set the GPIO to
use power_signal_interrupt_S0.

BUG=chrome-os-partner:49274
BRANCH=glados
TEST=echo freeze > /sys/power/state
Unfortunately currently SLP_S0_L is not asserting so this is difficult
to actually test the EC behavior

Change-Id: I302da7735c9622975e0386a0b4542f41c7231df9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/324567
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Duncan Laurie
2016-01-29 10:57:32 -08:00
committed by chrome-bot
parent 4f6f505900
commit b7cf464b86
2 changed files with 3 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
board/chell/board.h
View File

@@ -53,6 +53,7 @@
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
#define CONFIG_POWER_S0IX
#define CONFIG_PWM
#define CONFIG_PWM_KBLIGHT
/* All data won't fit in data RAM. So, moving boundary slightly. */
@@ -132,7 +133,7 @@
#undef CONFIG_CONSOLE_CMDHELP
#undef DEFERRABLE_MAX_COUNT
#define DEFERRABLE_MAX_COUNT 13
#define DEFERRABLE_MAX_COUNT 14
#ifndef __ASSEMBLER__

2
board/chell/gpio.inc
View File

@@ -14,7 +14,7 @@ GPIO_INT(POWER_BUTTON_L, PIN(35), GPIO_INT_BOTH, power_button_interrupt)
GPIO_INT(RSMRST_L_PGOOD, PIN(63), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S4_L, PIN(200), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S3_L, PIN(206), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PCH_SLP_S0_L, PIN(211), GPIO_INT_BOTH, power_signal_interrupt_S0)
GPIO_INT(PCH_SLP_SUS_L, PIN(12), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(PMIC_INT_L, PIN(50), GPIO_INT_FALLING, power_signal_interrupt)
GPIO_INT(PD_MCU_INT, PIN(122), GPIO_INT_FALLING | GPIO_PULL_UP, pd_mcu_interrupt)