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cr50: re-generate register descriptions

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New aliases are created automatically, there is no need to include
them in registers.h manually any more.

BRANCH=none
BUG=none
TEST=built and ran cr50 successfully

Change-Id: I9c12c9a66d231723f8c986dd0c598f1e03aaca3a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/311372
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This commit is contained in:
Vadim Bendebury
2015-11-06 09:23:09 -08:00
committed by chrome-bot
parent 54a2b91f3d
commit baed1d8672
2 changed files with 25 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
chip/g/cr50_fpga_regdefs.h
View File

@@ -574,40 +574,65 @@
#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 202
#define GC_INTERRUPTS_COUNT 218
#define GC_CAMO0_BASE_ADDR 0x40560000
#define GC_CAMO_BASE_ADDR 0x40560000
#define GC_CRYPTO0_BASE_ADDR 0x40420000
#define GC_CRYPTO_BASE_ADDR 0x40420000
#define GC_DMA0_BASE_ADDR 0x40430000
#define GC_DMA_BASE_ADDR 0x40430000
#define GC_FLASH0_BASE_ADDR 0x40720000
#define GC_FLASH_BASE_ADDR 0x40720000
#define GC_FUSE0_BASE_ADDR 0x40450000
#define GC_FUSE_BASE_ADDR 0x40450000
#define GC_GLOBALSEC_BASE_ADDR 0x40090000
#define GC_GPIO0_BASE_ADDR 0x40200000
#define GC_GPIO_BASE_ADDR 0x40200000
#define GC_GPIO1_BASE_ADDR 0x40210000
#define GC_I2C0_BASE_ADDR 0x40630000
#define GC_I2C_BASE_ADDR 0x40630000
#define GC_I2C1_BASE_ADDR 0x40640000
#define GC_I2CS0_BASE_ADDR 0x40530000
#define GC_I2CS_BASE_ADDR 0x40530000
#define GC_KEYMGR0_BASE_ADDR 0x40570000
#define GC_KEYMGR_BASE_ADDR 0x40570000
#define GC_PINMUX_BASE_ADDR 0x40060000
#define GC_PMU_BASE_ADDR 0x40000000
#define GC_M3_BASE_ADDR 0xe0000000
#define GC_RBOX0_BASE_ADDR 0x40550000
#define GC_RBOX_BASE_ADDR 0x40550000
#define GC_RDD0_BASE_ADDR 0x40440000
#define GC_RDD_BASE_ADDR 0x40440000
#define GC_RTC0_BASE_ADDR 0x400a0000
#define GC_RTC_BASE_ADDR 0x400a0000
#define GC_SPI0_BASE_ADDR 0x40700000
#define GC_SPI_BASE_ADDR 0x40700000
#define GC_SPI1_BASE_ADDR 0x40710000
#define GC_SPS0_BASE_ADDR 0x40510000
#define GC_SPS_BASE_ADDR 0x40510000
#define GC_SWDP0_BASE_ADDR 0x40520000
#define GC_SWDP_BASE_ADDR 0x40520000
#define GC_TEMP0_BASE_ADDR 0x40400000
#define GC_TEMP_BASE_ADDR 0x40400000
#define GC_TIMEHS0_BASE_ADDR 0x40650000
#define GC_TIMEHS_BASE_ADDR 0x40650000
#define GC_TIMEHS1_BASE_ADDR 0x40660000
#define GC_TIMELS0_BASE_ADDR 0x40540000
#define GC_TIMELS_BASE_ADDR 0x40540000
#define GC_TIMEUS0_BASE_ADDR 0x40670000
#define GC_TIMEUS_BASE_ADDR 0x40670000
#define GC_TRNG0_BASE_ADDR 0x40410000
#define GC_TRNG_BASE_ADDR 0x40410000
#define GC_UART0_BASE_ADDR 0x40600000
#define GC_UART_BASE_ADDR 0x40600000
#define GC_UART1_BASE_ADDR 0x40610000
#define GC_UART2_BASE_ADDR 0x40620000
#define GC_USB0_BASE_ADDR 0x40300000
#define GC_USB_BASE_ADDR 0x40300000
#define GC_VOLT0_BASE_ADDR 0x40460000
#define GC_VOLT_BASE_ADDR 0x40460000
#define GC_WATCHDOG0_BASE_ADDR 0x40500000
#define GC_WATCHDOG_BASE_ADDR 0x40500000
#define GC_XO0_BASE_ADDR 0x400b0000
#define GC_XO_BASE_ADDR 0x400b0000
#define GC_CAMO_BREACH_COUNT_OFFSET 0x0
#define GC_CAMO_BREACH_COUNT_DEFAULT 0x0
#define GC_CAMO_CLEAR_COUNTER_OFFSET 0x4

21
chip/g/registers.h
View File

@@ -20,27 +20,6 @@
*/
#define GC_MODULE_OFFSET 0x10000
#define GC_AES_BASE_ADDR GC_AES0_BASE_ADDR
#define GC_CAMO_BASE_ADDR GC_CAMO0_BASE_ADDR
#define GC_FLASH_BASE_ADDR GC_FLASH0_BASE_ADDR
#define GC_GPIO_BASE_ADDR GC_GPIO0_BASE_ADDR
#define GC_I2C_BASE_ADDR GC_I2C0_BASE_ADDR
#define GC_I2CS_BASE_ADDR GC_I2CS0_BASE_ADDR
#define GC_RBOX_BASE_ADDR GC_RBOX0_BASE_ADDR
#define GC_RTC_BASE_ADDR GC_RTC0_BASE_ADDR
#define GC_SHA_BASE_ADDR GC_SHA0_BASE_ADDR
#define GC_SPI_BASE_ADDR GC_SPI0_BASE_ADDR
#define GC_SPS_BASE_ADDR GC_SPS0_BASE_ADDR
#define GC_SWDP_BASE_ADDR GC_SWDP0_BASE_ADDR
#define GC_TEMP_BASE_ADDR GC_TEMP0_BASE_ADDR
#define GC_TIMEHS_BASE_ADDR GC_TIMEHS0_BASE_ADDR
#define GC_TIMELS_BASE_ADDR GC_TIMELS0_BASE_ADDR
#define GC_TRNG_BASE_ADDR GC_TRNG0_BASE_ADDR
#define GC_UART_BASE_ADDR GC_UART0_BASE_ADDR
#define GC_USB_BASE_ADDR GC_USB0_BASE_ADDR
#define GC_WATCHDOG_BASE_ADDR GC_WATCHDOG0_BASE_ADDR
#define GC_XO_BASE_ADDR GC_XO0_BASE_ADDR
#define GBASE(mname) \
GC_ ## mname ## _BASE_ADDR
#define GOFFSET(mname, rname) \