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mec1322: More code space in RAM

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1. No need for loader data ram
2. 97K code size
3. shifting down RO/RW image location in RAM by 1Kbyte.
   (loader code space: 4k to 3k)

BUG=none
TEST=1. build image with big code additions.(like low power idle patch)
        and check if there is flash size related error message.
     2. check if EC's RO image can boot from loader.
     3. use EC console command, "sysjump RO/RW" and check if it works.
     4. Verified in Cyan and Kunimitsu.
BRANCH=none

Change-Id: Ie4daf44cdba944e3e58894ca80183fcdb0fdbc7c
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302149
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Kyoung Kim
2015-09-17 15:56:48 -07:00
committed by chrome-bot
parent e1b26d02d6
commit bd1cb857c4
4 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
chip/mec1322/config_chip.h
View File

@@ -54,8 +54,8 @@
#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \
CONFIG_MEC_SRAM_BASE_START)
/* 2k RAM for Loader */
#define CONFIG_RAM_SIZE_LOADER 0x00000800
/* 0k RAM for Loader */
#define CONFIG_RAM_SIZE_LOADER 0x00000000
/* 24k RAM for RO /RW */
#define CONFIG_RAM_SIZE_RORW 0x00006000

4
chip/mec1322/config_flash_layout.h
View File

@@ -28,7 +28,7 @@
/* Loader resides at the beginning of program memory */
#define CONFIG_LOADER_MEM_OFF 0
#define CONFIG_LOADER_SIZE 0x1000
#define CONFIG_LOADER_SIZE 0xC00
/* Write protect Loader and RO Image */
#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF
@@ -44,7 +44,7 @@
*/
#define CONFIG_RO_MEM_OFF (CONFIG_LOADER_MEM_OFF + \
CONFIG_LOADER_SIZE)
#define CONFIG_RO_SIZE (96 * 1024)
#define CONFIG_RO_SIZE (97 * 1024)
#define CONFIG_RW_MEM_OFF CONFIG_RO_MEM_OFF
#define CONFIG_RW_SIZE CONFIG_RO_SIZE

2
chip/mec1322/lfw/ec_lfw.ld
View File

@@ -10,7 +10,7 @@
MEMORY
{
VECTOR(r ) : ORIGIN = 0x100000, LENGTH = 24
SRAM (xrw) : ORIGIN = 0x100018, LENGTH = 0x1000 - LENGTH(VECTOR)
SRAM (xrw) : ORIGIN = 0x100018, LENGTH = 0xC00 - LENGTH(VECTOR)
}
/*

2
chip/mec1322/util/pack_ec.py
View File

@@ -18,7 +18,7 @@ LOAD_ADDR = 0x100000
HEADER_SIZE = 0x140
SPI_CLOCK_LIST = [48, 24, 12, 8]
SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b]
IMAGE_SIZE = 96 * 1024
IMAGE_SIZE = 97 * 1024
CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15,
0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d]