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Define load addresses using macros

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This patch defines load addresses of regions using macros to increase
readability.

BUG=none
BRANCH=none
TEST=Diff firmware_image.lds before and after the change.

Change-Id: I24a13f4676b194efb748522f03c3134d1568f5ae
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/566940
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
This commit is contained in:
Daisuke Nojiri
2017-07-11 09:28:08 -07:00
committed by chrome-bot
parent a9c26a97ef
commit bd85364542
1 changed files with 25 additions and 21 deletions
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46
common/firmware_image.lds.S
View File

@@ -6,6 +6,29 @@
#include "config.h"
#include "rwsig.h"
#ifdef NPCX_RO_HEADER
/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header
* or some struture which doesn't belong to FW */
#define IMAGE_RO_AT (CONFIG_PROGRAM_MEMORY_BASE + \
CONFIG_EC_PROTECTED_STORAGE_OFF)
/* npcx uses *STORAGE_OFF to plan the layout of flash image */
#define IMAGE_RW_AT (CONFIG_PROGRAM_MEMORY_BASE + \
CONFIG_EC_WRITABLE_STORAGE_OFF + \
CONFIG_RW_STORAGE_OFF)
#elif (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
#define IMAGE_RO_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF)
/* This is applicable to ECs in which RO and RW execution is
mapped to the same location but we still have to generate an ec.bin with RO
and RW images at different Flash offset */
#define IMAGE_RW_AT (CONFIG_PROGRAM_MEMORY_BASE + \
CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
#else
#define IMAGE_RO_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF)
#define IMAGE_RW_AT (CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF)
#endif
OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
OUTPUT_ARCH(BFD_ARCH)
MEMORY
@@ -14,14 +37,7 @@ MEMORY
}
SECTIONS
{
#if defined(NPCX_RO_HEADER)
/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header
* or some struture which doesn't belong to FW */
.image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_PROTECTED_STORAGE_OFF\
) {
#else
.image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF) {
#endif
.image.RO : AT(IMAGE_RO_AT) {
*(.image.RO)
} > FLASH =0xff
@@ -44,19 +60,7 @@ SECTIONS
} > FLASH =0xff
#endif
#if defined(NPCX_RO_HEADER)
/* npcx uses *STORAGE_OFF to plan the layout of flash image */
.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_EC_WRITABLE_STORAGE_OFF \
+ CONFIG_RW_STORAGE_OFF) {
#elif (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF)
/* This is applicable to ECs in which RO and RW execution is
mapped to the same location but we still have to generate an ec.bin with RO
and RW images at different Flash offset */
.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF + \
CONFIG_RO_SIZE) {
#else
.image.RW : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RW_MEM_OFF) {
#endif
.image.RW : AT(IMAGE_RW_AT) {
*(.image.RW)
} > FLASH =0xff
#ifdef CONFIG_RWSIG_TYPE_RWSIG