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Remove obsolete EC targets

Browse Source 
This is needed to allow cleanup and refactoring of the EC codebase in
ToT.  All of these boards use firmware from branches and uploaded to
BCS, so they don't actually care that ToT can't build their firmware.

BUG=chromium:493866
TEST=build on the following using cbuildbot:
    daisy-paladin
    falco-paladin
    link-paladin
    nyan-paladin
    peppy-paladin
    samus-paladin
    squawks-paladin
    daisy_spring-paladin
CQ-DEPEND=CL:274121,CL:274127
BRANCH=none

Change-Id: I19598843755ded7b2385cc712ef463e5de4411b8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/274121
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This commit is contained in:
Randall Spangler
2015-05-29 13:51:49 -07:00
committed by ChromeOS Commit Bot
parent e856db1258
commit bdc680d8ed
126 changed files with 1 additions and 10311 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
board/falco/Makefile
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../../Makefile

46
board/falco/battery.c
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#define SB_SHIP_MODE_DATA 0x0010
static const struct battery_info info = {
.voltage_max = 8400,
.voltage_normal = 7400,
.voltage_min = 6000,
/* Pre-charge values. */
.precharge_current = 256, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 45,
.discharging_min_c = -10,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
int rv;
/* Ship mode command must be sent twice. */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHIP_MODE_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_MANUFACTURER_ACCESS, SB_SHIP_MODE_DATA);
}

154
board/falco/board.c
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* EC for Falco board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "backlight.h"
#include "board.h"
#include "charger.h"
#include "common.h"
#include "driver/temp_sensor/g781.h"
#include "extpower.h"
#include "fan.h"
#include "gpio.h"
#include "host_command.h"
#include "i2c.h"
#include "jtag.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "peci.h"
#include "power.h"
#include "power_button.h"
#include "registers.h"
#include "switch.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "thermal.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_PP5000_PGOOD, 1, "PGOOD_PP5000"},
{GPIO_PP1350_PGOOD, 1, "PGOOD_PP1350"},
{GPIO_PP1050_PGOOD, 1, "PGOOD_PP1050"},
{GPIO_VCORE_PGOOD, 1, "PGOOD_VCORE"},
{GPIO_PCH_SLP_S0_L, 1, "SLP_S0#_DEASSERTED"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3#_DEASSERTED"},
{GPIO_PCH_SLP_S5_L, 1, "SLP_S5#_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
const struct adc_t adc_channels[] = {
/* EC internal temperature is calculated by
* 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
* = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
*/
{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
/* IOUT == ICMNT is on PE3/AIN0 */
/* We have 0.01-ohm resistors, and IOUT is 20X the differential
* voltage, so 1000mA ==> 200mV.
* ADC returns 0x000-0xFFF, which maps to 0.0-3.3V (as configured).
* mA = 1000 * ADC_VALUE / ADC_READ_MAX * 3300 / 200
*/
{"ChargerCurrent", LM4_ADC_SEQ1, 33000, ADC_READ_MAX * 2, 0,
LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
/* AC Adapter ID voltage (mv) */
{"AdapterIDVoltage", LM4_ADC_SEQ2, 3300, ADC_READ_MAX, 0,
LM4_AIN(11), 0x06 /* IE0 | END0 */, LM4_GPIO_B, (1<<5)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_t fans[] = {
{.flags = FAN_USE_RPM_MODE,
.rpm_min = 1000,
.rpm_start = 1000,
.rpm_max = 5050,
.ch = 2,
.pgood_gpio = GPIO_PP5000_PGOOD,
.enable_gpio = -1,
},
};
BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"batt_chg", 0, 100},
{"lvds", 1, 100},
{"thermal", 5, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
const struct temp_sensor_t temp_sensors[] = {
{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0, 2},
{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
{"G781Internal", TEMP_SENSOR_TYPE_BOARD, g781_get_val,
G781_IDX_INTERNAL, 4},
{"G781External", TEMP_SENSOR_TYPE_BOARD, g781_get_val,
G781_IDX_EXTERNAL, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
/* Only the AP affects the thermal limits and fan speed. */
{ {C_TO_K(95), C_TO_K(97), C_TO_K(99)}, C_TO_K(55), C_TO_K(85)},
{ {0, 0, 0}, 0, 0},
{ {0, 0, 0}, 0, 0},
{ {0, 0, 0}, 0, 0},
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
struct keyboard_scan_config keyscan_config = {
.output_settle_us = 40,
.debounce_down_us = 6 * MSEC,
.debounce_up_us = 30 * MSEC,
.scan_period_us = 1500,
.min_post_scan_delay_us = 1000,
.poll_timeout_us = SECOND,
.actual_key_mask = {
0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8 /* full set */
},
};
/**
* Discharge battery when on AC power for factory test.
*/
int board_discharge_on_ac(int enable)
{
return charger_discharge_on_ac(enable);
}
/*
* Take a nice smooth ramp and make it all chunky.
* And never turn it off. Bah. That'll do wonders for battery life.
*/
#ifdef CONFIG_FAN_RPM_CUSTOM
int fan_percent_to_rpm(int fan, int pct)
{
const int FAN_MAX = fans[fan].rpm_max;
const int FAN_MIN = fans[fan].rpm_min;
const int NUM_STEPS = 7;
const int m = 100 * 100 / NUM_STEPS;
const int m0 = m / 200;
int chunky = 100 * (pct + m0) / m;
return FAN_MIN + (FAN_MAX - FAN_MIN) * m * chunky / 10000;
}
#endif /* CONFIG_FAN_RPM_CUSTOM */

127
board/falco/board.h
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Configuration for Falco mainboard */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V1
#define CONFIG_CHARGER_BQ24738
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHIPSET_CAN_THROTTLE
#define CONFIG_CHIPSET_HASWELL
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
#define CONFIG_CMD_GSV
#define CONFIG_EXTPOWER_FALCO
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FANS 1
#define CONFIG_KEYBOARD_BOARD_CONFIG
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_PECI_TJMAX 100
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_SWITCH_DEDICATED_RECOVERY
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_G781
#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PP3300_DX_EN
#define CONFIG_UART_HOST 2
#define CONFIG_USB_PORT_POWER_DUMB
#define CONFIG_VBOOT_HASH
#define CONFIG_WIRELESS
#undef DEFERRABLE_MAX_COUNT
#define DEFERRABLE_MAX_COUNT 9
#ifndef __ASSEMBLER__
/* I2C ports */
#define I2C_PORT_BATTERY 0
#define I2C_PORT_CHARGER 0
#define I2C_PORT_LVDS 1
#define I2C_PORT_THERMAL 5
/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
#define KB_SCAN_ROW_IRQ LM4_IRQ_GPIOK
#define KB_SCAN_ROW_GPIO LM4_GPIO_K
/* Host connects to keyboard controller module via LPC */
#define HOST_KB_BUS_LPC
/* USB ports */
#define USB_PORT_COUNT 2
#include "gpio_signal.h"
/* power signal definitions */
enum power_signal {
X86_PGOOD_PP5000 = 0,
X86_PGOOD_PP1350,
X86_PGOOD_PP1050,
X86_PGOOD_VCORE,
X86_SLP_S0_DEASSERTED,
X86_SLP_S3_DEASSERTED,
X86_SLP_S5_DEASSERTED,
X86_SLP_SUS_DEASSERTED,
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */
#define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, about half max */
#define CONFIG_CHARGER_TIMEOUT_HOURS 10 /* Max time to charge battery, hours */
enum adc_channel {
/* EC internal die temperature in degrees K. */
ADC_CH_EC_TEMP = 0,
/* Charger current in mA. */
ADC_CH_CHARGER_CURRENT,
/* AC Adapter ID voltage in mV */
ADC_AC_ADAPTER_ID_VOLTAGE,
ADC_CH_COUNT
};
enum temp_sensor_id {
/* CPU die temperature via PECI */
TEMP_SENSOR_CPU_PECI = 0,
/* EC internal temperature sensor */
TEMP_SENSOR_EC_INTERNAL,
/* G781 internal and external sensors */
TEMP_SENSOR_I2C_G781_INTERNAL,
TEMP_SENSOR_I2C_G781_EXTERNAL,
TEMP_SENSOR_COUNT
};
/**
* LCD VCC enable interrupt.
*/
void lcdvcc_interrupt(enum gpio_signal signal);
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
/* Discharge battery when on AC power for factory test. */
int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

12
board/falco/build.mk
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# -*- makefile -*-
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is TI Stellaris LM4
CHIP:=lm4
board-y=board.o battery.o led.o panel.o

27
board/falco/ec.tasklist
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' is the name of the task
* 'r' is the main routine of the task
* 'd' is an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

102
board/falco/gpio.inc
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/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(POWER_BUTTON_L, PIN(A, 2), GPIO_INT_BOTH_DSLEEP, power_button_interrupt) /* Power button */
GPIO_INT(LID_OPEN, PIN(A, 3), GPIO_INT_BOTH_DSLEEP, lid_interrupt) /* Lid switch */
GPIO_INT(AC_PRESENT, PIN(H, 3), GPIO_INT_BOTH_DSLEEP, extpower_interrupt) /* AC power present */
GPIO_INT(PCH_BKLTEN, PIN(M, 3), GPIO_INT_BOTH, backlight_interrupt) /* Backlight enable signal from PCH */
GPIO_INT(PCH_SLP_S0_L, PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0# signal from PCH */
GPIO_INT(PCH_SLP_S3_L, PIN(G, 7), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S3# signal from PCH */
GPIO_INT(PCH_SLP_S5_L, PIN(H, 1), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S5# signal from PCH */
GPIO_INT(PCH_SLP_SUS_L, PIN(G, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_SUS# signal from PCH */
GPIO_INT(PP1050_PGOOD, PIN(H, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.05V */
GPIO_INT(PP1350_PGOOD, PIN(H, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.35V (DRAM) */
GPIO_INT(PP5000_PGOOD, PIN(N, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 5V */
GPIO_INT(VCORE_PGOOD, PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on core VR */
GPIO_INT(PCH_EDP_VDD_EN, PIN(J, 1), GPIO_INT_BOTH, lcdvcc_interrupt) /* PCH wants EDP enabled */
GPIO_INT(RECOVERY_L, PIN(A, 5), GPIO_PULL_UP | GPIO_INT_BOTH, switch_interrupt) /* Recovery signal from servo */
GPIO_INT(WP_L, PIN(A, 4), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */
GPIO_INT(JTAG_TCK, PIN(C, 0), GPIO_DEFAULT, jtag_interrupt) /* JTAG clock input */
GPIO_INT(UART0_RX, PIN(A, 0), GPIO_PULL_UP | GPIO_INT_BOTH_DSLEEP, uart_deepsleep_interrupt) /* UART0 RX input */
/* Other inputs */
GPIO(FAN_ALERT_L, PIN(B, 0), GPIO_INPUT) /* From thermal sensor */
GPIO(PCH_SUSWARN_L, PIN(G, 2), GPIO_INT_BOTH) /* SUSWARN# signal from PCH */
GPIO(USB1_OC_L, PIN(E, 7), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(USB2_OC_L, PIN(E, 0), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(BOARD_VERSION1, PIN(Q, 5), GPIO_INPUT) /* Board version stuffing resistor 1 */
GPIO(BOARD_VERSION2, PIN(Q, 6), GPIO_INPUT) /* Board version stuffing resistor 2 */
GPIO(BOARD_VERSION3, PIN(Q, 7), GPIO_INPUT) /* Board version stuffing resistor 3 */
GPIO(CPU_PGOOD, PIN(C, 4), GPIO_INPUT) /* Power good to the CPU */
/* Outputs; all unasserted by default except for reset signals */
GPIO(CPU_PROCHOT, PIN(B, 1), GPIO_OUT_LOW) /* Force CPU to think it's overheated */
GPIO(PP1350_EN, PIN(H, 5), GPIO_OUT_LOW) /* Enable 1.35V supply */
GPIO(PP3300_DSW_GATED_EN, PIN(J, 3), GPIO_OUT_LOW) /* Enable DSW rails */
GPIO(PP3300_DX_EN, PIN(J, 2), GPIO_OUT_LOW) /* Enable power to lots of peripherals */
GPIO(PP3300_LTE_EN, PIN(D, 2), GPIO_OUT_LOW) /* Enable LTE radio */
GPIO(PP3300_WLAN_EN, PIN(J, 0), GPIO_OUT_LOW) /* Enable WiFi power */
GPIO(SUSP_VR_EN, PIN(C, 7), GPIO_OUT_LOW) /* Enable 1.05V regulator */
GPIO(VCORE_EN, PIN(C, 5), GPIO_OUT_LOW) /* Stuffing option - not connected */
GPIO(PP5000_EN, PIN(H, 7), GPIO_OUT_LOW) /* Enable 5V supply */
GPIO(SYS_PWROK, PIN(H, 2), GPIO_OUT_LOW) /* EC thinks everything is up and ready */
GPIO(WLAN_OFF_L, PIN(J, 4), GPIO_OUT_LOW) /* Disable WiFi radio */
GPIO(CHARGE_L, PIN(E, 6), GPIO_OUT_LOW) /* Allow battery to charge when on AC */
GPIO(ENABLE_BACKLIGHT, PIN(M, 7), GPIO_OUT_LOW) /* Enable backlight power */
GPIO(ENABLE_TOUCHPAD, PIN(N, 1), GPIO_OUT_LOW) /* Enable touchpad power */
GPIO(ENTERING_RW, PIN(D, 3), GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(PCH_DPWROK, PIN(G, 0), GPIO_OUT_LOW) /* Indicate when VccDSW is good */
/*
* HDA_SDO is technically an output, but we need to leave it as an
* input until we drive it high. So can't use open-drain (HI_Z).
*/
GPIO(PCH_HDA_SDO, PIN(G, 1), GPIO_INPUT) /* HDA_SDO signal to PCH; when high, ME ignores security descriptor */
GPIO(PCH_WAKE_L, PIN(F, 0), GPIO_OUT_HIGH) /* Wake signal from EC to PCH */
GPIO(PCH_NMI_L, PIN(F, 2), GPIO_OUT_HIGH) /* Non-maskable interrupt pin to PCH */
GPIO(PCH_PWRBTN_L, PIN(H, 0), GPIO_OUT_HIGH) /* Power button output to PCH */
GPIO(PCH_PWROK, PIN(F, 5), GPIO_OUT_LOW) /* PWROK / APWROK signals to PCH */
/*
* PL6 is one of 4 pins on the EC which can't be used in open-drain
* mode. To work around this PCH_RCIN_L is set to an input. It will
* only be set to an output when it needs to be driven to 0.
*/
GPIO(PCH_RCIN_L, PIN(L, 6), GPIO_INPUT) /* RCIN# line to PCH (for 8042 emulation) */
GPIO(PCH_RSMRST_L, PIN(F, 1), GPIO_OUT_LOW) /* Reset PCH resume power plane logic */
GPIO(PCH_SMI_L, PIN(F, 4), GPIO_ODR_HIGH) /* System management interrupt to PCH */
GPIO(TOUCHSCREEN_RESET_L, PIN(N, 7), GPIO_OUT_LOW) /* Reset touch screen */
GPIO(EC_EDP_VDD_EN, PIN(J, 5), GPIO_OUT_LOW) /* Enable EDP (passthru from PCH) */
GPIO(LPC_CLKRUN_L, PIN(M, 2), GPIO_ODR_HIGH) /* Dunno. Probably important, though. */
GPIO(USB1_ENABLE, PIN(E, 4), GPIO_OUT_LOW) /* USB port 1 output power enable */
GPIO(USB2_ENABLE, PIN(D, 5), GPIO_OUT_LOW) /* USB port 2 output power enable */
GPIO(PCH_SUSACK_L, PIN(F, 3), GPIO_OUT_HIGH) /* Acknowledge PCH SUSWARN# signal */
GPIO(PCH_RTCRST_L, PIN(F, 6), GPIO_ODR_HIGH) /* Not supposed to be here */
GPIO(PCH_SRTCRST_L, PIN(F, 7), GPIO_ODR_HIGH) /* Not supposed to be here */
GPIO(PWR_LED_L, PIN(N, 6), GPIO_OUT_HIGH) /* Power LED */
GPIO(KB_LED_EN, PIN(D, 4), GPIO_OUT_LOW) /* Keyboard LED */
GPIO(BAT_LED0, PIN(D, 0), GPIO_OUT_LOW) /* Battery charger status */
GPIO(BAT_LED1, PIN(D, 1), GPIO_OUT_LOW) /* Battery charger status */
ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART0 */
ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_I2C, 0) /* I2C1 SCL */
ALTERNATE(PIN_MASK(A, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C1 SDA */
ALTERNATE(PIN_MASK(B, 0x04), 3, MODULE_I2C, 0) /* I2C0 SCL */
ALTERNATE(PIN_MASK(B, 0x08), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C0 SDA */
ALTERNATE(PIN_MASK(B, 0x40), 3, MODULE_I2C, 0) /* I2C5 SCL */
ALTERNATE(PIN_MASK(B, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C5 SDA */
ALTERNATE(PIN_MASK(G, 0x30), 1, MODULE_UART, 0) /* UART2 */
ALTERNATE(PIN_MASK(J, 0x40), 1, MODULE_PECI, 0) /* PECI Tx */
ALTERNATE(PIN_MASK(J, 0x80), 0, MODULE_PECI, GPIO_ANALOG) /* PECI Rx */
ALTERNATE(PIN_MASK(L, 0x3f), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(M, 0x33), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(N, 0x0c), 1, MODULE_PWM_FAN, 0) /* FAN0PWM2 */

103
board/falco/led.c
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control for Falco.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "extpower.h"
#include "gpio.h"
#include "hooks.h"
enum led_color {
LED_OFF = 0,
LED_WHITE,
LED_AMBER,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
static int bat_led_set_color(enum led_color color)
{
switch (color) {
case LED_OFF:
gpio_set_level(GPIO_BAT_LED0, 1);
gpio_set_level(GPIO_BAT_LED1, 1);
break;
case LED_WHITE:
gpio_set_level(GPIO_BAT_LED0, 1);
gpio_set_level(GPIO_BAT_LED1, 0);
break;
case LED_AMBER:
gpio_set_level(GPIO_BAT_LED0, 0);
gpio_set_level(GPIO_BAT_LED1, 1);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
static int pwr_led_set_color(enum led_color color)
{
switch (color) {
case LED_OFF:
gpio_set_level(GPIO_PWR_LED_L, 1);
break;
case LED_WHITE:
gpio_set_level(GPIO_PWR_LED_L, 0);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
/* Called by hook task every 250mSec */
static void led_tick(void)
{
static int ticks;
uint32_t chflags = charge_get_flags();
ticks++;
if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
pwr_led_set_color(LED_OFF);
else if (chipset_in_state(CHIPSET_STATE_ON))
pwr_led_set_color(LED_WHITE);
else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
pwr_led_set_color((ticks & 0x4) ? LED_WHITE : LED_OFF);
/* Battery LED is solid white if AC connected, unless the battery is
* is charging or there is an error. */
bat_led_set_color(extpower_is_present() ? LED_WHITE : LED_OFF);
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
bat_led_set_color(LED_AMBER);
break;
case PWR_STATE_DISCHARGE:
/* See crosbug.com/p/22159. There's a 3% difference
* between the battery level seen by the kernel and what's
* really going on, so if they want to see 12%, we use 15%.
* Hard code this number here, because this only affects the
* LED color, not the battery charge state. */
if (charge_get_percent() < 15)
bat_led_set_color((ticks & 0x4) ? LED_WHITE : LED_OFF);
break;
case PWR_STATE_ERROR:
bat_led_set_color((ticks & 0x2) ? LED_WHITE : LED_OFF);
break;
case PWR_STATE_IDLE:
if (chflags & CHARGE_FLAG_FORCE_IDLE)
bat_led_set_color((ticks & 0x4) ? LED_AMBER : LED_OFF);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);

131
board/falco/panel.c
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "common.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "lid_switch.h"
/*
* Falco needs a 420ms delay for a 0->1 transition of the PCH's backlight
* enable signal. The reason is that Falco has a LVDS bridge which controls
* all the other signals for the panel except the backlight. In order to
* meet the penel power sequencing requirements a delay needs to be added.
*
* Additionally the LCDVCC needs to be delayed on a 0->1 transition of the
* PCH's EDP VDD enable signal to meet the panel specification.
*/
#define BL_ENABLE_DELAY_US 420000 /* 420 ms delay */
#define LCDVCC_ENABLE_DELAY_US 270000 /* 270 ms delay */
static int backlight_deferred_value;
static void set_backlight_value(void)
{
gpio_set_level(GPIO_ENABLE_BACKLIGHT, backlight_deferred_value);
}
DECLARE_DEFERRED(set_backlight_value);
/**
* Update backlight state.
*/
static void update_backlight(void)
{
int pch_value;
pch_value = gpio_get_level(GPIO_PCH_BKLTEN);
/* Immediately disable the backlight when the lid is closed or the PCH
* is instructing the backlight to be disabled. */
if (!lid_is_open() || !pch_value) {
/* If there was a scheduled callback pending make sure it picks
* up the disabled value. */
backlight_deferred_value = 0;
gpio_set_level(GPIO_ENABLE_BACKLIGHT, 0);
/* Cancel pending hook */
hook_call_deferred(&set_backlight_value, -1);
return;
}
/* Handle a 0->1 transition by calling a deferred hook. */
if (pch_value && !backlight_deferred_value) {
backlight_deferred_value = 1;
hook_call_deferred(&set_backlight_value, BL_ENABLE_DELAY_US);
}
}
DECLARE_HOOK(HOOK_LID_CHANGE, update_backlight, HOOK_PRIO_DEFAULT);
void backlight_interrupt(enum gpio_signal signal)
{
update_backlight();
}
/**
* Host command to toggle backlight.
*/
static int switch_command_enable_backlight(struct host_cmd_handler_args *args)
{
const struct ec_params_switch_enable_backlight *p = args->params;
gpio_set_level(GPIO_ENABLE_BACKLIGHT, p->enabled);
return EC_RES_SUCCESS;
}
DECLARE_HOST_COMMAND(EC_CMD_SWITCH_ENABLE_BKLIGHT,
switch_command_enable_backlight, 0);
static int lcdvcc_en_deferred_value;
static void set_lcdvcc_en_value(void)
{
gpio_set_level(GPIO_EC_EDP_VDD_EN, lcdvcc_en_deferred_value);
}
DECLARE_DEFERRED(set_lcdvcc_en_value);
void lcdvcc_interrupt(enum gpio_signal signal)
{
int pch_value;
pch_value = gpio_get_level(GPIO_PCH_EDP_VDD_EN);
/* Immediately disable the LCDVCC when the PCH indicates as such. */
if (!pch_value) {
/* If there was a scheduled callback pending make sure it picks
* up the disabled value. */
lcdvcc_en_deferred_value = 0;
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
/* Cancel pending hook */
hook_call_deferred(&set_lcdvcc_en_value, -1);
return;
}
/* Handle a 0->1 transition by calling a deferred hook. */
if (pch_value && !lcdvcc_en_deferred_value) {
lcdvcc_en_deferred_value = 1;
hook_call_deferred(&set_lcdvcc_en_value,
LCDVCC_ENABLE_DELAY_US);
}
}
/**
* Initialize panel module.
*/
static void panel_init(void)
{
/* Set initial deferred value and signal to the current PCH signal. */
backlight_deferred_value = gpio_get_level(GPIO_PCH_BKLTEN);
set_backlight_value();
update_backlight();
gpio_enable_interrupt(GPIO_PCH_BKLTEN);
/* The interrupt is enabled for the GPIO_PCH_EDP_VDD_EN in the
* chipset_haswell.c compilation unit. Initially set the value
* to whatever it current is reading. */
lcdvcc_en_deferred_value = gpio_get_level(GPIO_PCH_EDP_VDD_EN);
set_lcdvcc_en_value();
}
DECLARE_HOOK(HOOK_INIT, panel_init, HOOK_PRIO_DEFAULT);

1
board/firefly/Makefile
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@@ -1 +0,0 @@
../../Makefile

124
board/firefly/board.c
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@@ -1,124 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Firefly board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "i2c.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
#include "usb_pd.h"
#include "util.h"
/* Debounce time for voltage buttons */
#define BUTTON_DEBOUNCE_US (100 * MSEC)
static enum gpio_signal button_pressed;
/* Handle debounced button press */
static void button_deferred(void)
{
int mv;
/* bounce ? */
if (gpio_get_level(button_pressed) != 0)
return;
switch (button_pressed) {
case GPIO_SW_PP20000:
mv = 20000;
break;
case GPIO_SW_PP12000:
mv = 12000;
break;
case GPIO_SW_PP5000:
mv = 5000;
break;
default:
mv = -1;
}
pd_request_source_voltage(0, mv);
ccprintf("Button %d = %d => Vout=%d mV\n",
button_pressed, gpio_get_level(button_pressed), mv);
}
DECLARE_DEFERRED(button_deferred);
void button_event(enum gpio_signal signal)
{
button_pressed = signal;
/* reset debounce time */
hook_call_deferred(button_deferred, BUTTON_DEBOUNCE_US);
}
void vbus_event(enum gpio_signal signal)
{
ccprintf("VBUS! =%d\n", gpio_get_level(signal));
task_wake(TASK_ID_PD);
}
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
/* Remap USART DMA to match the USART driver */
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1 (PD RX)
* Chan 3 : SPI1_TX (PD TX)
* Chan 4 : USART1_TX
* Chan 5 : USART1_RX
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10);/* Remap USART1 RX/TX DMA */
}
#include "gpio_list.h"
/* ADC channels */
const struct adc_t adc_channels[] = {
/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(2)},
/* VBUS voltage sensing is behind a 10K/100K voltage divider */
[ADC_CH_VBUS_SENSE] = {"VBUS", 36300, 4096, 0, STM32_AIN(5)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
static void board_init(void)
{
gpio_enable_interrupt(GPIO_SW_PP20000);
gpio_enable_interrupt(GPIO_SW_PP12000);
gpio_enable_interrupt(GPIO_SW_PP5000);
/* Enable interrupts on VBUS transitions. */
gpio_enable_interrupt(GPIO_VBUS_WAKE);
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
static int command_volt(int argc, char **argv)
{
int millivolt = -1;
if (argc >= 2) {
char *e;
millivolt = strtoi(argv[1], &e, 10) * 1000;
}
ccprintf("Request Vout=%d mV\n", millivolt);
pd_request_source_voltage(0, millivolt);
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(volt, command_volt,
"[5|12|20]",
"set voltage through USB PD",
NULL);

74
board/firefly/board.h
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@@ -1,74 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Firefly board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* the UART console is on USART1 (PA9/PA10) */
#define CONFIG_UART_CONSOLE 1
/* Optional features */
#define CONFIG_STM_HWTIMER32
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_INTERNAL_COMP
#define CONFIG_USB_PD_PORT_COUNT 1
#define CONFIG_USB_PD_TCPC
#define CONFIG_USB_PD_TCPM_STUB
#define CONFIG_ADC
#define CONFIG_HW_CRC
#define CONFIG_I2C
#define CONFIG_BOARD_PRE_INIT
#undef CONFIG_WATCHDOG_HELP
#undef CONFIG_LID_SWITCH
#undef CONFIG_TASK_PROFILING
/* I2C ports configuration */
#define I2C_PORT_SLAVE 0
/*
* Allow dangerous commands all the time, since we don't have a write protect
* switch.
*/
#define CONFIG_SYSTEM_UNLOCKED
#ifndef __ASSEMBLER__
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_ADC 3
#include "gpio_signal.h"
/* ADC signal */
enum adc_channel {
ADC_CH_CC1_PD = 0,
ADC_CH_CC2_PD,
ADC_CH_VBUS_SENSE,
/* Number of ADC channels */
ADC_CH_COUNT
};
/* we are acting only as a sink */
#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
/* we are never a source : don't care about power supply */
#define PD_POWER_SUPPLY_TURN_ON_DELAY 0 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 0 /* us */
/* Define typical operating power and max power */
#define PD_OPERATING_POWER_MW 1000
#define PD_MAX_POWER_MW 1500
#define PD_MAX_CURRENT_MA 300
#define PD_MAX_VOLTAGE_MV 20000
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

14
board/firefly/build.mk
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@@ -1,14 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F072CBU6
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f07x
board-y=board.o
board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o

22
board/firefly/ec.tasklist
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@@ -1,22 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE)

66
board/firefly/gpio.inc
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@@ -1,66 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(VBUS_WAKE, PIN(C, 13), GPIO_INT_BOTH, vbus_event)
/* Buttons */
GPIO_INT(SW_PP20000, PIN(B, 10), GPIO_INT_FALLING, button_event)
GPIO_INT(SW_PP12000, PIN(B, 11), GPIO_INT_FALLING, button_event)
GPIO_INT(SW_PP5000, PIN(B, 12), GPIO_INT_FALLING, button_event)
/* PD RX/TX */
GPIO(USB_CC1_PD, PIN(A, 0), GPIO_ANALOG)
GPIO(PD_REF1, PIN(A, 1), GPIO_ANALOG)
GPIO(USB_CC2_PD, PIN(A, 2), GPIO_ANALOG)
GPIO(PD_REF2, PIN(A, 3), GPIO_ANALOG)
GPIO(PD_CC1_TX_EN, PIN(A, 4), GPIO_ODR_HIGH)
GPIO(PD_CC2_TX_EN, PIN(A, 15), GPIO_ODR_HIGH)
GPIO(PD_CLK_OUT, PIN(B, 9), GPIO_OUT_LOW)
GPIO(PD_CC1_TX_DATA, PIN(A, 6), GPIO_INPUT)
GPIO(PD_CC2_TX_DATA, PIN(B, 4), GPIO_INPUT)
GPIO(PD_CLK_IN, PIN(B, 3), GPIO_INPUT)
/* CCx device pull-downs */
GPIO(PD_CC1_DEVICE, PIN(B, 13), GPIO_ODR_LOW)
GPIO(PD_CC2_DEVICE, PIN(B, 14), GPIO_ODR_LOW)
/* ADC */
GPIO(VBUS_SENSE, PIN(A, 5), GPIO_ANALOG)
/* LEDs control */
GPIO(LED_PP20000, PIN(B, 0), GPIO_OUT_LOW)
GPIO(LED_PP12000, PIN(B, 1), GPIO_OUT_LOW)
GPIO(LED_PP5000, PIN(B, 2), GPIO_OUT_LOW)
/* Slave I2C port */
GPIO(I2C_INT_L, PIN(B, 8), GPIO_ODR_HIGH)
/*
* I2C pins should be configured as inputs until I2C module is
* initialized. This will avoid driving the lines unintentionally.
*/
GPIO(I2C_SCL, PIN(B, 6), GPIO_INPUT)
GPIO(I2C_SDA, PIN(B, 7), GPIO_INPUT)
/* Test points */
GPIO(TP_A8, PIN(A, 8), GPIO_ODR_HIGH)
GPIO(TP_A13, PIN(A, 13), GPIO_ODR_HIGH)
GPIO(TP_A14, PIN(A, 14), GPIO_ODR_HIGH)
GPIO(TP_B15, PIN(B, 15), GPIO_ODR_HIGH)
GPIO(TP_C14, PIN(C, 14), GPIO_ODR_HIGH)
GPIO(TP_C15, PIN(C, 15), GPIO_ODR_HIGH)
GPIO(TP_F0, PIN(F, 0), GPIO_ODR_HIGH)
GPIO(TP_F1, PIN(F, 1), GPIO_ODR_HIGH)
/* Unimplemented signals which we need to emulate for now */
UNIMPLEMENTED(ENTERING_RW)
UNIMPLEMENTED(WP_L)
ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1: SCK(PB3) */
ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0) /* TIM17_CH1: PB9) */
ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, GPIO_PULL_UP) /* USART1: PA9/PA10 */
ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 */

137
board/firefly/usb_pd_config.h
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 17
#define TIM_CLOCK_PD_RX_C0 1
#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
/* Timer channel */
#define TIM_RX_CCR_C0 1
#define TIM_TX_CCR_C0 1
/* RX timer capture/compare register */
#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
#define TIM_RX_CCR_REG(p) TIM_CCR_C0
/* TX and RX timer register */
#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
#define TIM_REG_TX(p) TIM_REG_TX_C0
#define TIM_REG_RX(p) TIM_REG_RX_C0
/* use the hardware accelerator for CRC */
#define CONFIG_HW_CRC
/* TX is using SPI1 on PB3/PB4 or PA6 */
#define SPI_REGS(p) STM32_SPI1_REGS
static inline void spi_enable_clock(int port)
{
STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
}
#define DMAC_SPI_TX(p) STM32_DMAC_CH3
/* RX is using COMP1 triggering TIM1 CH1 */
#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
#define CMP2OUTSEL STM32_COMP_CMP2OUTSEL_TIM1_IC1
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) ((1 << 21) | (1 << 22))
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
#define DMAC_TIM_RX(p) STM32_DMAC_CH2
/* the pins used for communication need to be hi-speed */
static inline void pd_set_pins_speed(int port)
{
/* 40 MHz pin speed on SPI1 PA6/7 */
STM32_GPIO_OSPEEDR(GPIO_A) |= 0x0000F000;
/* 40 MHz pin speed on SPI1 PB3/4/5 */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x00000FC0;
/* 40 MHz pin speed on TIM17_CH1 (PB9) */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C0000;
}
/* Reset SPI peripheral used for TX */
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI1 */
STM32_RCC_APB2RSTR |= (1 << 12);
STM32_RCC_APB2RSTR &= ~(1 << 12);
}
/* Drive the CC line from the TX block */
static inline void pd_tx_enable(int port, int polarity)
{
/* put SPI function on TX pin */
if (polarity) /* PB4 is SPI1 MISO */
gpio_set_alternate_function(GPIO_B, 0x0010, 0);
else /* PA6 is SPI1 MISO */
gpio_set_alternate_function(GPIO_A, 0x0040, 0);
/* set the low level reference */
gpio_set_level(polarity ? GPIO_PD_CC2_TX_EN : GPIO_PD_CC1_TX_EN, 0);
}
/* Put the TX driver in Hi-Z state */
static inline void pd_tx_disable(int port, int polarity)
{
/* put SPI TX in Hi-Z */
if (polarity)
gpio_set_alternate_function(GPIO_B, 0x0010, -1);
else
gpio_set_alternate_function(GPIO_A, 0x0040, -1);
/* put the low level reference in Hi-Z */
gpio_set_level(polarity ? GPIO_PD_CC2_TX_EN : GPIO_PD_CC1_TX_EN, 1);
}
/* we know the plug polarity, do the right configuration */
static inline void pd_select_polarity(int port, int polarity)
{
/* use the right comparator */
STM32_COMP_CSR =
(STM32_COMP_CSR & ~(STM32_COMP_CMP1EN | STM32_COMP_CMP2EN))
| (polarity ? STM32_COMP_CMP2EN : STM32_COMP_CMP1EN);
}
/* Initialize pins used for TX and put them in Hi-Z */
static inline void pd_tx_init(void)
{
/* Configure SCK pin */
gpio_config_module(MODULE_USB_PD, 1);
}
static inline void pd_set_host_mode(int port, int enable)
{
}
static inline void pd_config_init(int port, uint8_t power_role)
{
/* Initialize TX pins and put them in Hi-Z */
pd_tx_init();
}
static inline int pd_adc_read(int port, int cc)
{
if (cc == 0)
return adc_read_channel(ADC_CH_CC1_PD);
else
return adc_read_channel(ADC_CH_CC2_PD);
}
#endif /* __USB_PD_CONFIG_H */

151
board/firefly/usb_pd_policy.c
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@@ -1,151 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "adc.h"
#include "board.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_pd.h"
#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
/* Acceptable margin between requested VBUS and measured value */
#define MARGIN_MV 400 /* mV */
#define PDO_FIXED_FLAGS (PDO_FIXED_EXTERNAL)
/* we are not acting as a source */
const uint32_t pd_src_pdo[] = {
PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
};
const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
/* Fake PDOs : we just want our pre-defined voltages */
const uint32_t pd_snk_pdo[] = {
PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
PDO_FIXED(12000, 500, PDO_FIXED_FLAGS),
PDO_FIXED(20000, 500, PDO_FIXED_FLAGS),
};
const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
void pd_set_input_current_limit(int port, uint32_t max_ma,
uint32_t supply_voltage)
{
/* No battery, nothing to do */
return;
}
int pd_is_valid_input_voltage(int mv)
{
/* Any voltage less than the max is allowed */
return 1;
}
int pd_check_requested_voltage(uint32_t rdo)
{
/* Never acting as a source */
return EC_ERROR_INVAL;
}
void pd_transition_voltage(int idx)
{
/* No operation: sink only */
}
int pd_set_power_supply_ready(int port)
{
/* Never acting as a source */
return EC_ERROR_INVAL;
}
void pd_power_supply_reset(int port)
{
}
int pd_snk_is_vbus_provided(int port)
{
/* VBUS_WAKE is broken (not detecting 5V), use the ADC instead */
return adc_read_channel(ADC_CH_VBUS_SENSE) > 4000;
}
int pd_board_checks(void)
{
static int blinking;
int vbus;
int led5 = 0, led12 = 0, led20 = 0;
unsigned select_mv = pd_get_max_voltage();
/* LED blinking state for the default indicator */
blinking = (blinking + 1) & 3;
vbus = adc_read_channel(ADC_CH_VBUS_SENSE);
if (select_mv > 0) {
/* is current VBUS voltage matching the request ? */
int diff = vbus - select_mv;
int correct = (diff < MARGIN_MV) && (diff > -MARGIN_MV);
/*
* turn on the LED if the voltage is correct
* or we are in on-period of the duty cycle.
*/
int led_value = correct || !blinking;
/* decide which LED is used */
switch (select_mv) {
case 5000:
led5 = led_value;
break;
case 12000:
led12 = led_value;
break;
case 20000:
led20 = led_value;
break;
}
}
/* switch LEDs */
gpio_set_level(GPIO_LED_PP5000, led5);
gpio_set_level(GPIO_LED_PP12000, led12);
gpio_set_level(GPIO_LED_PP20000, led20);
return EC_SUCCESS;
}
int pd_check_power_swap(int port)
{
/* Always refuse power swap */
return 0;
}
int pd_check_data_swap(int port, int data_role)
{
/* Always refuse data swap */
return 0;
}
void pd_execute_data_swap(int port, int data_role)
{
/* Do nothing */
}
void pd_check_pr_role(int port, int pr_role, int flags)
{
}
void pd_check_dr_role(int port, int dr_role, int flags)
{
}
int pd_custom_vdm(int port, int cnt, uint32_t *payload,
uint32_t **rpayload)
{
return 0;
}

1
board/fruitpie/Makefile
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../../Makefile

235
board/fruitpie/board.c
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@@ -1,235 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Fruitpie board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "common.h"
#include "console.h"
#include "ec_version.h"
#include "gpio.h"
#include "hooks.h"
#include "i2c.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
#include "usb.h"
#include "usb_pd.h"
#include "util.h"
#include "driver/tsu6721.h"
void rohm_event(enum gpio_signal signal)
{
ccprintf("ROHM!\n");
}
void vbus_event(enum gpio_signal signal)
{
ccprintf("VBUS!\n");
}
void tsu_event(enum gpio_signal signal)
{
ccprintf("TSU!\n");
}
#include "gpio_list.h"
/* Initialize board. */
static void board_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
/* Remap SPI2 to DMA channels 6 and 7 */
STM32_SYSCFG_CFGR1 |= (1 << 24);
}
DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
/* ADC channels */
const struct adc_t adc_channels[] = {
/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
[ADC_CH_CC1_PD] = {"CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
[ADC_CH_CC2_PD] = {"CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100,
GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
const void * const usb_strings[] = {
[USB_STR_DESC] = usb_string_desc,
[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
[USB_STR_PRODUCT] = USB_STRING_DESC("FruitPie"),
[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
};
BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
int board_set_debug(int enable)
{
timestamp_t timeout;
int rv = EC_SUCCESS;
if (enable) {
/* Disable the PD module */
gpio_config_module(MODULE_USB_PD, 0);
/* Suspend the USB PD task */
pd_set_suspend(0, 1);
/* Decrease BCDv1.2 timer to 0.6s */
tsu6721_write(TSU6721_REG_TIMER, 0x05);
timeout.val = get_time().val + DEBUG_SWITCH_TIMEOUT_MSEC;
/* Wait for power to be detected to allow switching debug mux */
while (!(tsu6721_read(TSU6721_REG_DEV_TYPE3) & 0x74)) {
if (get_time().val > timeout.val)
return EC_ERROR_TIMEOUT;
/* Not already powered by cable, turn on regulator */
gpio_set_level(GPIO_USB_C_5V_EN, 1);
ccputs("Sleeping for 1s, waiting for TSU6721...\n");
usleep(1000*MSEC);
}
/* Enable manual switching */
rv = tsu6721_mux(TSU6721_MUX_USB);
if (rv)
return rv;
/* Switch debug mux */
tsu6721_set_pins(TSU6721_PIN_MANUAL2_BOOT);
/* Set pins PD_CLK_IN, PD_TX_DATA, and
* VCONN1_EN to alternate function. */
/* Set pin PD_TX_EN (NSS) to general purpose output mode. */
STM32_GPIO_MODER(GPIO_B) &= ~0xff000000;
STM32_GPIO_MODER(GPIO_B) |= 0xa9000000;
/* Set all four pins to alternate function 0 */
STM32_GPIO_AFRH(GPIO_B) &= ~(0xffff0000);
/* Set all four pins to output push-pull */
STM32_GPIO_OTYPER(GPIO_B) &= ~(0xf000);
/* Set pullup on PD_TX_EN */
STM32_GPIO_PUPDR(GPIO_B) |= 0x1000000;
/* Set all four pins to high speed */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0xff000000;
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
/* Enable clocks to SPI2 module */
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
} else {
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
/* Set all but VCONN1_EN to input mode */
STM32_GPIO_MODER(GPIO_B) &= ~0x3f000000;
/* Unset pullup on PD_TX_EN/SPI_NSS */
gpio_set_flags(GPIO_PD_TX_EN, GPIO_OUT_LOW);
/* Turn off debug mux */
tsu6721_set_pins(0);
/* Disable manual switching */
rv = tsu6721_mux(TSU6721_MUX_AUTO);
if (rv)
return rv;
/* Disable power on USB_C_5V_EN pin */
gpio_set_level(GPIO_USB_C_5V_EN, 0);
/* Restore BCDv1.2 timer to 1.6s */
tsu6721_write(TSU6721_REG_TIMER, 0x15);
/* Restore the USB PD task */
pd_set_suspend(0, 0);
}
return rv;
}
static int command_debug(int argc, char **argv)
{
char *e;
int v;
if (argc < 2)
return EC_ERROR_PARAM_COUNT;
v = strtoi(argv[1], &e, 0);
if (*e)
return EC_ERROR_PARAM1;
ccprintf("Setting debug: %d...\n", v);
board_set_debug(v);
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(debugset, command_debug, NULL, "Set debug mode", NULL);
void board_set_usb_mux(int port, enum typec_mux mux,
enum usb_switch usb, int polarity)
{
/* reset everything */
gpio_set_level(GPIO_SS1_EN_L, 1);
gpio_set_level(GPIO_SS2_EN_L, 1);
gpio_set_level(GPIO_DP_MODE, 0);
gpio_set_level(GPIO_SS1_USB_MODE_L, 1);
gpio_set_level(GPIO_SS2_USB_MODE_L, 1);
if (mux == TYPEC_MUX_NONE)
/* everything is already disabled, we can return */
return;
if (mux == TYPEC_MUX_USB || mux == TYPEC_MUX_DOCK) {
/* USB 3.0 uses 2 superspeed lanes */
gpio_set_level(polarity ? GPIO_SS2_USB_MODE_L :
GPIO_SS1_USB_MODE_L, 0);
}
if (mux == TYPEC_MUX_DP || mux == TYPEC_MUX_DOCK) {
/* DP uses available superspeed lanes (x2 or x4) */
gpio_set_level(GPIO_DP_POLARITY_L, !polarity);
gpio_set_level(GPIO_DP_MODE, 1);
}
/* switch on superspeed lanes */
gpio_set_level(GPIO_SS1_EN_L, 0);
gpio_set_level(GPIO_SS2_EN_L, 0);
}
int board_get_usb_mux(int port, const char **dp_str, const char **usb_str)
{
int has_ss = !gpio_get_level(GPIO_SS1_EN_L);
int has_usb = !gpio_get_level(GPIO_SS1_USB_MODE_L) ||
!gpio_get_level(GPIO_SS2_USB_MODE_L);
int has_dp = !!gpio_get_level(GPIO_DP_MODE);
if (has_dp)
*dp_str = gpio_get_level(GPIO_DP_POLARITY_L) ? "DP1" : "DP2";
else
*dp_str = NULL;
if (has_usb)
*usb_str = gpio_get_level(GPIO_SS1_USB_MODE_L) ?
"USB2" : "USB1";
else
*usb_str = NULL;
return has_ss;
}

139
board/fruitpie/board.h
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@@ -1,139 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Fruitpie board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* the UART console is on USART2 (PA14/PA15) */
#undef CONFIG_UART_CONSOLE
#define CONFIG_UART_CONSOLE 2
/* Optional features */
#define CONFIG_STM_HWTIMER32
#define CONFIG_USB
#define CONFIG_USB_POWER_DELIVERY
#define CONFIG_USB_PD_ALT_MODE
#define CONFIG_USB_PD_ALT_MODE_DFP
#define CONFIG_USB_PD_CUSTOM_VDM
#define CONFIG_USB_PD_DUAL_ROLE
#define CONFIG_USB_PD_INTERNAL_COMP
#define CONFIG_USB_PD_PORT_COUNT 1
#define CONFIG_USB_PD_TCPC
#define CONFIG_USB_PD_TCPM_STUB
#define CONFIG_USBC_SS_MUX
#define CONFIG_USBC_VCONN
#define CONFIG_ADC
#define CONFIG_HW_CRC
#define CONFIG_I2C
#define CONFIG_BATTERY_SMART
#define CONFIG_USB_SWITCH_TSU6721
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SIZE 8388608
#define CONFIG_SPI_FLASH_W25Q64
#define CONFIG_SPI_MASTER_PORT 2
#define CONFIG_SPI_CS_GPIO GPIO_PD_TX_EN
#undef CONFIG_WATCHDOG_HELP
#undef CONFIG_LID_SWITCH
#undef CONFIG_TASK_PROFILING
/* I2C ports configuration */
#define I2C_PORT_MASTER 1
#define I2C_PORT_BATTERY I2C_PORT_MASTER
#define I2C_PORT_CHARGER I2C_PORT_MASTER
#define I2C_PORT_SLAVE 0
/* Charger configuration */
#define CONFIG_CHARGER
#undef CONFIG_CHARGER_V1
#define CONFIG_CHARGER_BQ24773
#define CONFIG_CHARGER_SENSE_RESISTOR 5 /* milliOhms */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* milliOhms */
#define CONFIG_CHARGER_INPUT_CURRENT 512 /* mA */
#define CONFIG_CHARGER_ILIM_PIN_DISABLED /* external ILIM pin disabled */
/* USB configuration */
#define CONFIG_USB_PID 0x5009
/* By default, enable all console messages excepted USB */
#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_USB))
/*
* Allow dangerous commands all the time, since we don't have a write protect
* switch.
*/
#define CONFIG_SYSTEM_UNLOCKED
#ifndef __ASSEMBLER__
/*
* Timeout to wait for TSU6721 to detect power. Set to double the BCD timer.
*/
#define DEBUG_SWITCH_TIMEOUT_MSEC (1200*MSEC)
/*
* Used to set GPIO's and clock to SPI module used for debug
*
* @param enable Whether to enable or disable debug
*/
int board_set_debug(int enable);
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_ADC 3
#include "gpio_signal.h"
/* ADC signal */
enum adc_channel {
ADC_CH_CC1_PD = 0,
ADC_CH_CC2_PD,
/* Number of ADC channels */
ADC_CH_COUNT
};
/* USB string indexes */
enum usb_strings {
USB_STR_DESC = 0,
USB_STR_VENDOR,
USB_STR_PRODUCT,
USB_STR_VERSION,
USB_STR_COUNT
};
/* Standard-current Rp */
#define PD_SRC_VNC PD_SRC_DEF_VNC_MV
#define PD_SRC_RD_THRESHOLD PD_SRC_DEF_RD_THRESH_MV
/* start as a sink in case we have no other power supply/battery */
#define PD_DEFAULT_STATE PD_STATE_SNK_DISCONNECTED
/* delay necessary for the voltage transition on the power supply */
#define PD_POWER_SUPPLY_TURN_ON_DELAY 50000 /* us */
#define PD_POWER_SUPPLY_TURN_OFF_DELAY 50000 /* us */
/* Define typical operating power and max power */
#define PD_OPERATING_POWER_MW 1000
#define PD_MAX_POWER_MW 60000
#define PD_MAX_CURRENT_MA 3000
#define PD_MAX_VOLTAGE_MV 20000
#endif /* !__ASSEMBLER__ */
/* USB interface indexes (use define rather than enum to expand them) */
#define USB_IFACE_MS 0
#define USB_IFACE_COUNT 1
/* USB endpoint indexes (use define rather than enum to expand them) */
#define USB_EP_CONTROL 0
#define USB_EP_MS_TX 1
#define USB_EP_MS_RX 2
#define USB_EP_COUNT 3
#endif /* __BOARD_H */

14
board/fruitpie/build.mk
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@@ -1,14 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F072B
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f07x
board-y=board.o
board-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o

22
board/fruitpie/ec.tasklist
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@@ -1,22 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(PD, pd_task, NULL, TASK_STACK_SIZE)

73
board/fruitpie/gpio.inc
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@@ -1,73 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
GPIO_INT(VBUS_WAKE, PIN(B, 5), GPIO_INT_BOTH, vbus_event)
GPIO_INT(MASTER_I2C_INT_L, PIN(C, 13), GPIO_INT_FALLING, tsu_event)
GPIO_INT(ALERT_L, PIN(A, 2), GPIO_INT_FALLING, rohm_event)
/* PD RX/TX */
GPIO(USB_CC1_PD, PIN(A, 0), GPIO_ANALOG)
GPIO(PD_REF1, PIN(A, 1), GPIO_ANALOG)
GPIO(PD_REF2, PIN(A, 3), GPIO_ANALOG)
GPIO(USB_CC2_PD, PIN(A, 4), GPIO_ANALOG)
GPIO(PD_CLK_OUT, PIN(B, 9), GPIO_OUT_LOW)
GPIO(PD_TX_EN, PIN(B, 12), GPIO_OUT_LOW)
GPIO(PD_TX_DATA, PIN(B, 14), GPIO_OUT_LOW)
#if 0
GPIO(PD_CLK_IN, PIN(B, 13), GPIO_OUT_LOW)
#endif
/* Power and muxes control */
GPIO(PP5000_EN, PIN(A, 5), GPIO_OUT_HIGH)
GPIO(CC_HOST, PIN(A, 6), GPIO_OUT_LOW)
GPIO(CHARGE_EN_L, PIN(A, 8), GPIO_OUT_LOW)
GPIO(USB_C_5V_EN, PIN(A, 10), GPIO_OUT_LOW)
GPIO(VCONN1_EN, PIN(B, 15), GPIO_OUT_LOW)
GPIO(VCONN2_EN, PIN(C, 14), GPIO_OUT_LOW)
GPIO(SS1_EN_L, PIN(A, 9), GPIO_OUT_HIGH)
GPIO(SS2_EN_L, PIN(B, 4), GPIO_OUT_HIGH)
GPIO(SS2_USB_MODE_L, PIN(B, 3), GPIO_OUT_HIGH)
GPIO(SS1_USB_MODE_L, PIN(B, 8), GPIO_OUT_HIGH)
GPIO(DP_MODE, PIN(C, 15), GPIO_OUT_LOW)
GPIO(DP_POLARITY_L, PIN(A, 7), GPIO_OUT_HIGH)
/* Not used : no host on that bus */
GPIO(SLAVE_I2C_INT_L, PIN(B, 2), GPIO_ODR_HIGH)
/* Alternate functions */
#if 0
GPIO(USB_DM, PIN(A, 11), GPIO_ANALOG)
GPIO(USB_DP, PIN(A, 12), GPIO_ANALOG)
GPIO(UART_TX, PIN(A, 14), GPIO_OUT_LOW)
GPIO(UART_RX, PIN(A, 15), GPIO_OUT_LOW)
#endif
/*
* I2C pins should be configured as inputs until I2C module is
* initialized. This will avoid driving the lines unintentionally.
*/
GPIO(SLAVE_I2C_SCL, PIN(B, 6), GPIO_INPUT)
GPIO(SLAVE_I2C_SDA, PIN(B, 7), GPIO_INPUT)
GPIO(MASTER_I2C_SCL, PIN(B, 10), GPIO_INPUT)
GPIO(MASTER_I2C_SDA, PIN(B, 11), GPIO_INPUT)
/* Rohm BD92104 connections */
GPIO(USBPD_RST, PIN(B, 0), GPIO_OUT_LOW)
GPIO(USBPD_FORCE_OTG, PIN(B, 1), GPIO_OUT_LOW)
GPIO(USBPD_VIN_EN_L, PIN(F, 0), GPIO_OUT_HIGH)
/* Test points */
GPIO(TP9, PIN(A, 13), GPIO_ODR_HIGH)
GPIO(TP11, PIN(F, 1), GPIO_ODR_HIGH)
/* Unimplemented signals which we need to emulate for now */
UNIMPLEMENTED(ENTERING_RW)
UNIMPLEMENTED(WP_L)
ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2: SCK(PB13) */
ALTERNATE(PIN_MASK(B, 0x0200), 2, MODULE_USB_PD, 0) /* TIM17_CH1: PB9) */
ALTERNATE(PIN_MASK(A, 0xC000), 1, MODULE_UART, 0) /* USART2: PA14/PA15 */
ALTERNATE(PIN_MASK(B, 0x0cc0), 1, MODULE_I2C, 0) /* I2C SLAVE:PB6/7 MASTER:PB10/11 */

174
board/fruitpie/usb_pd_config.h
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@@ -1,174 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* USB Power delivery board configuration */
#ifndef __USB_PD_CONFIG_H
#define __USB_PD_CONFIG_H
/* Timer selection for baseband PD communication */
#define TIM_CLOCK_PD_TX_C0 17
#define TIM_CLOCK_PD_RX_C0 1
#define TIM_CLOCK_PD_TX(p) TIM_CLOCK_PD_TX_C0
#define TIM_CLOCK_PD_RX(p) TIM_CLOCK_PD_RX_C0
/* Timer channel */
#define TIM_RX_CCR_C0 1
#define TIM_TX_CCR_C0 1
/* RX timer capture/compare register */
#define TIM_CCR_C0 (&STM32_TIM_CCRx(TIM_CLOCK_PD_RX_C0, TIM_RX_CCR_C0))
#define TIM_RX_CCR_REG(p) TIM_CCR_C0
/* TX and RX timer register */
#define TIM_REG_TX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_TX_C0))
#define TIM_REG_RX_C0 (STM32_TIM_BASE(TIM_CLOCK_PD_RX_C0))
#define TIM_REG_TX(p) TIM_REG_TX_C0
#define TIM_REG_RX(p) TIM_REG_RX_C0
/* use the hardware accelerator for CRC */
#define CONFIG_HW_CRC
/* TX is using SPI2 on PB12-14 */
#define SPI_REGS(p) STM32_SPI2_REGS
static inline void spi_enable_clock(int port)
{
STM32_RCC_APB1ENR |= STM32_RCC_PB1_SPI2;
STM32_SYSCFG_CFGR1 |= 1 << 24; /* Remap SPI2 DMA */
}
#define DMAC_SPI_TX(p) STM32_DMAC_CH7
/* RX is using COMP1 triggering TIM1 CH1 */
#define CMP1OUTSEL STM32_COMP_CMP1OUTSEL_TIM1_IC1
#define CMP2OUTSEL 0
#define TIM_TX_CCR_IDX(p) TIM_TX_CCR_C0
#define TIM_RX_CCR_IDX(p) TIM_RX_CCR_C0
#define TIM_CCR_CS 1
#define EXTI_COMP_MASK(p) (1 << 21)
#define IRQ_COMP STM32_IRQ_COMP
/* triggers packet detection on comparator falling edge */
#define EXTI_XTSR STM32_EXTI_FTSR
#define DMAC_TIM_RX(p) STM32_DMAC_CH2
/* the pins used for communication need to be hi-speed */
static inline void pd_set_pins_speed(int port)
{
/* 40 MHz pin speed on SPI PB12/13/14 */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x3f000000;
/* 40 MHz pin speed on TIM17_CH1 (PB9) */
STM32_GPIO_OSPEEDR(GPIO_B) |= 0x000C0000;
}
/* Reset SPI peripheral used for TX */
static inline void pd_tx_spi_reset(int port)
{
/* Reset SPI2 */
STM32_RCC_APB1RSTR |= (1 << 14);
STM32_RCC_APB1RSTR &= ~(1 << 14);
}
/* Drive the CC line from the TX block */
static inline void pd_tx_enable(int port, int polarity)
{
/* TX_DATA on PB14 is now connected to SPI2 */
gpio_set_alternate_function(GPIO_B, 0x4000, 0);
gpio_set_level(GPIO_PD_TX_EN, 1);
}
/* Put the TX driver in Hi-Z state */
static inline void pd_tx_disable(int port, int polarity)
{
/* TX_DATA on PB14 is an output low GPIO to disable the FET */
STM32_GPIO_MODER(GPIO_B) = (STM32_GPIO_MODER(GPIO_B) & ~(3 << (2*14)))
| (1 << (2*14));
/*
* Tri-state the low side after the high side
* to ensure we are not going above Vnc
*/
gpio_set_level(GPIO_PD_TX_EN, 0);
}
/* we know the plug polarity, do the right configuration */
static inline void pd_select_polarity(int port, int polarity)
{
/* use the right comparator non inverted input for COMP1 */
STM32_COMP_CSR = (STM32_COMP_CSR & ~STM32_COMP_CMP1INSEL_MASK)
| STM32_COMP_CMP1EN
| (polarity ? STM32_COMP_CMP1INSEL_INM4
: STM32_COMP_CMP1INSEL_INM6);
}
/* Initialize pins used for TX and put them in Hi-Z */
static inline void pd_tx_init(void)
{
gpio_config_module(MODULE_USB_PD, 1);
}
static inline void pd_set_host_mode(int port, int enable)
{
/* We never charging in power source mode */
if (enable) {
gpio_set_level(GPIO_CHARGE_EN_L, 1);
} else {
/* Kill VBUS power supply */
gpio_set_level(GPIO_USB_C_5V_EN, 0);
/* Enable the charging path*/
gpio_set_level(GPIO_CHARGE_EN_L, 0);
}
gpio_set_level(GPIO_CC_HOST, enable);
}
/**
* Initialize various GPIOs and interfaces to safe state at start of pd_task.
*
* These include:
* VBUS, charge path based on power role.
* Physical layer CC transmit.
* VCONNs disabled.
*
* @param port USB-C port number
* @param power_role Power role of device
*/
static inline void pd_config_init(int port, uint8_t power_role)
{
/*
* Set CC pull resistors, and charge_en and vbus_en GPIOs to match
* the initial role.
*/
pd_set_host_mode(port, power_role);
/* Initialize TX pins and put them in Hi-Z */
pd_tx_init();
/* Reset mux ... for NONE polarity doesn't matter */
board_set_usb_mux(port, TYPEC_MUX_NONE, USB_SWITCH_DISCONNECT, 0);
gpio_set_level(GPIO_VCONN1_EN, 0);
gpio_set_level(GPIO_VCONN2_EN, 0);
}
static inline int pd_adc_read(int port, int cc)
{
if (cc == 0)
return adc_read_channel(ADC_CH_CC1_PD);
else
return adc_read_channel(ADC_CH_CC2_PD);
}
static inline void pd_set_vconn(int port, int polarity, int enable)
{
/* Set VCONN on the opposite CC line from the polarity */
gpio_set_level(polarity ? GPIO_VCONN1_EN :
GPIO_VCONN2_EN, enable);
}
#endif /* __USB_PD_CONFIG_H */

238
board/fruitpie/usb_pd_policy.c
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@@ -1,238 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include "charger.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "registers.h"
#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#include "usb_pd.h"
#define CPRINTF(format, args...) cprintf(CC_USBPD, format, ## args)
#define CPRINTS(format, args...) cprints(CC_USBPD, format, ## args)
#define PDO_FIXED_FLAGS (PDO_FIXED_EXTERNAL | PDO_FIXED_DUAL_ROLE | \
PDO_FIXED_DATA_SWAP)
const uint32_t pd_src_pdo[] = {
PDO_FIXED(5000, 3000, PDO_FIXED_FLAGS),
PDO_FIXED(12000, 3000, PDO_FIXED_FLAGS),
PDO_FIXED(20000, 3000, PDO_FIXED_FLAGS),
};
const int pd_src_pdo_cnt = ARRAY_SIZE(pd_src_pdo);
const uint32_t pd_snk_pdo[] = {
PDO_FIXED(5000, 500, PDO_FIXED_FLAGS),
PDO_BATT(5000, 20000, 15000),
PDO_VAR(5000, 20000, 3000),
};
const int pd_snk_pdo_cnt = ARRAY_SIZE(pd_snk_pdo);
void pd_set_input_current_limit(int port, uint32_t max_ma,
uint32_t supply_voltage)
{
int rv = charger_set_input_current(MAX(max_ma,
CONFIG_CHARGER_INPUT_CURRENT));
if (rv < 0)
CPRINTS("Failed to set input current limit for PD");
}
int pd_is_valid_input_voltage(int mv)
{
/* Any voltage less than the max is allowed */
return 1;
}
int pd_check_requested_voltage(uint32_t rdo)
{
int max_ma = rdo & 0x3FF;
int op_ma = (rdo >> 10) & 0x3FF;
int idx = rdo >> 28;
uint32_t pdo;
uint32_t pdo_ma;
if (!idx || idx > pd_src_pdo_cnt)
return EC_ERROR_INVAL; /* Invalid index */
/* check current ... */
pdo = pd_src_pdo[idx - 1];
pdo_ma = (pdo & 0x3ff);
if (op_ma > pdo_ma)
return EC_ERROR_INVAL; /* too much op current */
if (max_ma > pdo_ma)
return EC_ERROR_INVAL; /* too much max current */
CPRINTF("Requested %d V %d mA (for %d/%d mA)\n",
((pdo >> 10) & 0x3ff) * 50, (pdo & 0x3ff) * 10,
((rdo >> 10) & 0x3ff) * 10, (rdo & 0x3ff) * 10);
return EC_SUCCESS;
}
void pd_transition_voltage(int idx)
{
/* No-operation: we are always 5V */
}
int pd_set_power_supply_ready(int port)
{
/* provide VBUS */
gpio_set_level(GPIO_USB_C_5V_EN, 1);
return EC_SUCCESS; /* we are ready */
}
void pd_power_supply_reset(int port)
{
/* Kill VBUS */
gpio_set_level(GPIO_USB_C_5V_EN, 0);
}
int pd_snk_is_vbus_provided(int port)
{
return gpio_get_level(GPIO_VBUS_WAKE);
}
int pd_board_checks(void)
{
return EC_SUCCESS;
}
int pd_check_power_swap(int port)
{
/* Always allow power swap */
return 1;
}
int pd_check_data_swap(int port, int data_role)
{
/* Always allow data swap */
return 1;
}
void pd_execute_data_swap(int port, int data_role)
{
/* Do nothing */
}
void pd_check_pr_role(int port, int pr_role, int flags)
{
}
void pd_check_dr_role(int port, int dr_role, int flags)
{
}
/* ----------------- Vendor Defined Messages ------------------ */
const struct svdm_response svdm_rsp = {
.identity = NULL,
.svids = NULL,
.modes = NULL,
};
int pd_custom_vdm(int port, int cnt, uint32_t *payload,
uint32_t **rpayload)
{
int cmd = PD_VDO_CMD(payload[0]);
uint16_t dev_id = 0;
/* make sure we have some payload */
if (cnt == 0)
return 0;
switch (cmd) {
case VDO_CMD_VERSION:
/* guarantee last byte of payload is null character */
*(payload + cnt - 1) = 0;
CPRINTF("version: %s\n", (char *)(payload+1));
break;
case VDO_CMD_READ_INFO:
case VDO_CMD_SEND_INFO:
/* if last word is present, it contains lots of info */
if (cnt == 7) {
dev_id = VDO_INFO_HW_DEV_ID(payload[6]);
CPRINTF("DevId:%d.%d SW:%d RW:%d\n",
HW_DEV_ID_MAJ(dev_id),
HW_DEV_ID_MIN(dev_id),
VDO_INFO_SW_DBG_VER(payload[6]),
VDO_INFO_IS_RW(payload[6]));
}
/* copy hash */
if (cnt >= 6)
pd_dev_store_rw_hash(port, dev_id, payload + 1,
SYSTEM_IMAGE_UNKNOWN);
break;
}
return 0;
}
static int svdm_enter_dp_mode(int port, uint32_t mode_caps)
{
/* Only enter mode if device is DFP_D capable */
if (mode_caps & MODE_DP_SNK) {
CPRINTF("Entering mode w/ vdo = %08x\n", mode_caps);
return 0;
}
return -1;
}
static int dp_on;
static int svdm_dp_status(int port, uint32_t *payload)
{
payload[0] = VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_STATUS);
payload[1] = VDO_DP_STATUS(0, /* HPD IRQ ... not applicable */
0, /* HPD level ... not applicable */
0, /* exit DP? ... no */
0, /* usb mode? ... no */
0, /* multi-function ... no */
dp_on,
0, /* power low? ... no */
dp_on);
return 2;
};
static int svdm_dp_config(int port, uint32_t *payload)
{
board_set_usb_mux(port, TYPEC_MUX_DP, USB_SWITCH_CONNECT,
pd_get_polarity(port));
dp_on = 1;
payload[0] = VDO(USB_SID_DISPLAYPORT, 1, CMD_DP_CONFIG);
payload[1] = VDO_DP_CFG(MODE_DP_PIN_E, /* sink pins */
MODE_DP_PIN_E, /* src pins */
1, /* DPv1.3 signaling */
2); /* UFP connected */
return 2;
};
static int svdm_dp_attention(int port, uint32_t *payload)
{
return 1; /* ack */
}
static void svdm_exit_dp_mode(int port)
{
CPRINTF("Exiting mode\n");
/* return to safe config */
}
const struct svdm_amode_fx supported_modes[] = {
{
.svid = USB_SID_DISPLAYPORT,
.enter = &svdm_enter_dp_mode,
.status = &svdm_dp_status,
.config = &svdm_dp_config,
.attention = &svdm_dp_attention,
.exit = &svdm_exit_dp_mode,
},
};
const int supported_modes_cnt = ARRAY_SIZE(supported_modes);

1
board/jerry/Makefile
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@@ -1 +0,0 @@
../../Makefile

54
board/jerry/battery.c
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@@ -1,54 +0,0 @@
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "console.h"
#include "gpio.h"
#include "host_command.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHUTDOWN_DATA 0x0010
static const struct battery_info info = {
.voltage_max = 8400, /* mV */
.voltage_normal = 7400,
.voltage_min = 6000,
.precharge_current = 256, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 45,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
static int cutoff(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
}
int board_cut_off_battery(void)
{
return cutoff();
}

75
board/jerry/board.c
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@@ -1,75 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Veyron board-specific configuration */
#include "battery.h"
#include "chipset.h"
#include "common.h"
#include "extpower.h"
#include "gpio.h"
#include "i2c.h"
#include "keyboard_raw.h"
#include "lid_switch.h"
#include "power.h"
#include "power_button.h"
#include "power.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "spi.h"
#include "task.h"
#include "util.h"
#include "timer.h"
#include "charger.h"
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_SOC_POWER_GOOD, 1, "POWER_GOOD"},
{GPIO_SUSPEND_L, 1, "SUSPEND#_ASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{STM32_TIM(2), STM32_TIM_CH(3),
PWM_CONFIG_ACTIVE_LOW},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
/**
* Discharge battery when on AC power for factory test.
*/
int board_discharge_on_ac(int enable)
{
return charger_discharge_on_ac(enable);
}
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
/* Remap USART DMA to match the USART driver */
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1
* Chan 3 : SPI1_TX
* Chan 4 : USART1_TX
* Chan 5 : USART1_RX
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
}

91
board/jerry/board.h
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@@ -1,91 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Veyron board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_CHARGER
#define CONFIG_CHARGER_BQ24715
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_V2
#define CONFIG_CHIPSET_ROCKCHIP
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HOST_COMMAND_STATUS
#define CONFIG_I2C
#define CONFIG_KEYBOARD_COL2_INVERTED
#define CONFIG_KEYBOARD_PROTOCOL_MKBP
#define CONFIG_LED_COMMON
#define CONFIG_LED_POLICY_STD
#define CONFIG_LED_BAT_ACTIVE_LOW
#define CONFIG_LED_POWER_ACTIVE_LOW
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LOW_POWER_S0
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1
#define CONFIG_POWER_COMMON
#define CONFIG_PWM
#define CONFIG_SPI
#define CONFIG_STM_HWTIMER32
#define CONFIG_UART_RX_DMA
#define CONFIG_VBOOT_HASH
#undef CONFIG_WATCHDOG_HELP
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1 | STM32_PWR_CSR_EWUP6)
#ifndef __ASSEMBLER__
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* Keyboard output port list */
#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C
/* Single I2C port, where the EC is the master. */
#define I2C_PORT_MASTER 0
#define I2C_PORT_BATTERY I2C_PORT_MASTER
#define I2C_PORT_CHARGER I2C_PORT_MASTER
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_WATCHDOG 4
#include "gpio_signal.h"
enum power_signal {
RK_POWER_GOOD = 0,
RK_SUSPEND_ASSERTED,
/* Number of power signals */
POWER_SIGNAL_COUNT
};
enum pwm_channel {
PWM_CH_POWER_LED = 0,
/* Number of PWM channels */
PWM_CH_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* Input sensor resistor, mOhm */
/* Input current limit for 45W AC adapter:
* 45W/19V*85%=2013mA, choose the closest charger setting = 2048mA
*/
#define CONFIG_CHARGER_INPUT_CURRENT 2048 /* mA, based on Link HW design */
#define CONFIG_CHARGER_CURRENT_LIMIT 3000 /* PL102 inductor 3.0A(3.8A) */
/* Discharge battery when on AC power for factory test. */
int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

13
board/jerry/build.mk
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@@ -1,13 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F071RB
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f07x
board-y=board.o battery.o

23
board/jerry/ec.tasklist
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@@ -1,23 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK(n, r, d, s) where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

59
board/jerry/gpio.inc
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@@ -1,59 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(POWER_BUTTON_L, PIN(B, 5), GPIO_INT_BOTH, power_button_interrupt) /* wk6 */ /* active high, the name is for compatibility with existing code */
GPIO_INT(SOC_POWER_GOOD, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(LID_OPEN, PIN(C, 13), GPIO_INT_BOTH, lid_interrupt)
GPIO_INT(SUSPEND_L, PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INT_BOTH, spi_event)
GPIO_INT(AC_PRESENT, PIN(C, 6), GPIO_INT_BOTH | GPIO_PULL_UP, extpower_interrupt)
/* Keyboard inputs */
GPIO_INT(KB_IN00, PIN(C, 8), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN01, PIN(C, 9), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN07, PIN(D, 2), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
/* Other inputs */
GPIO(EC_WAKE, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN) /* wk1 */
GPIO(WP_L, PIN(B, 4), GPIO_INPUT)
/* Outputs */
GPIO(BAT_LED_RED, PIN(B, 11), GPIO_OUT_HIGH)
GPIO(BAT_LED_GREEN, PIN(A, 11), GPIO_OUT_HIGH)
GPIO(EC_BL_OVERRIDE, PIN(F, 1), GPIO_OUT_LOW)
GPIO(EC_INT, PIN(B, 9), GPIO_OUT_LOW)
GPIO(ENTERING_RW, PIN(F, 0), GPIO_OUT_LOW)
GPIO(I2C1_SCL, PIN(B, 6), GPIO_ODR_HIGH)
GPIO(I2C1_SDA, PIN(B, 7), GPIO_ODR_HIGH)
GPIO(KB_OUT00, PIN(B, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT01, PIN(B, 8), GPIO_KB_OUTPUT)
GPIO(KB_OUT02, PIN(B, 12), GPIO_OUT_LOW) /* Inverted from silegro */
GPIO(KB_OUT03, PIN(B, 13), GPIO_KB_OUTPUT)
GPIO(KB_OUT04, PIN(B, 14), GPIO_KB_OUTPUT)
GPIO(KB_OUT05, PIN(B, 15), GPIO_KB_OUTPUT)
GPIO(KB_OUT06, PIN(C, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT07, PIN(C, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT08, PIN(C, 2), GPIO_KB_OUTPUT)
GPIO(KB_OUT09, PIN(B, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT10, PIN(C, 5), GPIO_KB_OUTPUT)
GPIO(KB_OUT11, PIN(C, 4), GPIO_KB_OUTPUT)
GPIO(KB_OUT12, PIN(A, 13), GPIO_KB_OUTPUT)
GPIO(POWER_LED, PIN(A, 2), GPIO_OUT_HIGH)
GPIO(PMIC_PWRON, PIN(A, 12), GPIO_OUT_LOW)
GPIO(PMIC_RESET, PIN(B, 3), GPIO_OUT_LOW)
GPIO(PMIC_SOURCE_PWREN, PIN(B, 10), GPIO_OUT_LOW)
GPIO(PMIC_WARM_RESET_L, PIN(C, 3), GPIO_ODR_HIGH)
ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0)
ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0)

1
board/keyborg/Makefile
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@@ -1 +0,0 @@
../../Makefile

199
board/keyborg/board.c
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@@ -1,199 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Keyborg board-specific configuration */
#include "common.h"
#include "cpu.h"
#include "debug.h"
#include "master_slave.h"
#include "registers.h"
#include "spi_comm.h"
#include "system.h"
#include "task.h"
#include "touch_scan.h"
#include "util.h"
#include "version.h"
const struct ts_pin row_pins[] = {
{TS_GPIO_E, 0}, /* R1 */
{TS_GPIO_E, 4}, /* R2 */
{TS_GPIO_E, 8}, /* R3 */
{TS_GPIO_E, 1}, /* R4 */
{TS_GPIO_E, 11}, /* R5 */
{TS_GPIO_E, 12}, /* R6 */
{TS_GPIO_E, 15}, /* R7 */
{TS_GPIO_E, 13}, /* R8 */
{TS_GPIO_D, 3}, /* R9 */
{TS_GPIO_D, 4}, /* R10 */
{TS_GPIO_D, 5}, /* R11 */
{TS_GPIO_D, 0}, /* R12 */
{TS_GPIO_D, 6}, /* R13 */
{TS_GPIO_D, 8}, /* R14 */
{TS_GPIO_D, 11}, /* R15 */
{TS_GPIO_D, 10}, /* R16 */
{TS_GPIO_D, 12}, /* R17 */
{TS_GPIO_D, 13}, /* R18 */
{TS_GPIO_D, 14}, /* R19 */
{TS_GPIO_D, 15}, /* R20 */
{TS_GPIO_C, 8}, /* R21 */
{TS_GPIO_C, 7}, /* R22 */
{TS_GPIO_C, 15}, /* R23 */
{TS_GPIO_E, 6}, /* R24 */
{TS_GPIO_E, 5}, /* R25 */
{TS_GPIO_E, 2}, /* R26 */
{TS_GPIO_E, 3}, /* R27 */
{TS_GPIO_E, 10}, /* R28 */
{TS_GPIO_E, 9}, /* R29 */
{TS_GPIO_E, 14}, /* R30 */
{TS_GPIO_E, 7}, /* R31 */
{TS_GPIO_D, 2}, /* R32 */
{TS_GPIO_D, 7}, /* R33 */
{TS_GPIO_D, 1}, /* R34 */
{TS_GPIO_D, 9}, /* R35 */
{TS_GPIO_C, 5}, /* R36 */
{TS_GPIO_C, 6}, /* R37 */
{TS_GPIO_C, 10}, /* R38 */
{TS_GPIO_C, 13}, /* R39 */
{TS_GPIO_C, 14}, /* R40 */
{TS_GPIO_C, 12}, /* R41 */
};
BUILD_ASSERT(ARRAY_SIZE(row_pins) == ROW_COUNT);
const struct ts_pin col_pins[] = {
{TS_GPIO_B, 5}, /* C1 */
{TS_GPIO_H, 1}, /* C2 */
{TS_GPIO_H, 0}, /* C3 */
{TS_GPIO_H, 5}, /* C4 */
{TS_GPIO_H, 10}, /* C5 */
{TS_GPIO_H, 6}, /* C6 */
{TS_GPIO_H, 4}, /* C7 */
{TS_GPIO_H, 3}, /* C8 */
{TS_GPIO_H, 9}, /* C9 */
{TS_GPIO_H, 12}, /* C10 */
{TS_GPIO_H, 11}, /* C11 */
{TS_GPIO_H, 15}, /* C12 */
{TS_GPIO_H, 2}, /* C13 */
{TS_GPIO_H, 14}, /* C14 */
{TS_GPIO_G, 5}, /* C15 */
{TS_GPIO_G, 9}, /* C16 */
{TS_GPIO_G, 4}, /* C17 */
{TS_GPIO_G, 15}, /* C18 */
{TS_GPIO_G, 10}, /* C19 */
{TS_GPIO_G, 12}, /* C20 */
{TS_GPIO_G, 0}, /* C21 */
{TS_GPIO_G, 11}, /* C22 */
{TS_GPIO_B, 0}, /* C23 */
{TS_GPIO_G, 2}, /* C24 */
{TS_GPIO_G, 1}, /* C25 */
{TS_GPIO_A, 13}, /* C26 */
{TS_GPIO_A, 14}, /* C27 */
{TS_GPIO_B, 3}, /* C28 */
{TS_GPIO_A, 10}, /* Fake C29. C29 is used as UART Tx. */
{TS_GPIO_B, 8}, /* C30 */
{TS_GPIO_A, 10}, /* C31 */
{TS_GPIO_B, 1}, /* C32 */
{TS_GPIO_G, 13}, /* C33 */
{TS_GPIO_B, 7}, /* C34 */
{TS_GPIO_B, 2}, /* C35 */
{TS_GPIO_G, 14}, /* C36 */
{TS_GPIO_G, 3}, /* C37 */
{TS_GPIO_G, 7}, /* C38 */
{TS_GPIO_H, 13}, /* C39 */
{TS_GPIO_H, 7}, /* C40 */
{TS_GPIO_B, 4}, /* C41 */
{TS_GPIO_H, 8}, /* C42 */
{TS_GPIO_B, 6}, /* C43 */
{TS_GPIO_B, 9}, /* C44 */
{TS_GPIO_I, 10}, /* C45 */
{TS_GPIO_I, 11}, /* C46 */
{TS_GPIO_I, 9}, /* C47 */
{TS_GPIO_G, 8}, /* C48 */
{TS_GPIO_G, 6}, /* C49 */
{TS_GPIO_I, 4}, /* C50 */
{TS_GPIO_I, 3}, /* C51 */
{TS_GPIO_I, 5}, /* C52 */
{TS_GPIO_I, 14}, /* C53 */
{TS_GPIO_I, 12}, /* C54 */
{TS_GPIO_I, 8}, /* C55 */
{TS_GPIO_I, 6}, /* C56 */
{TS_GPIO_I, 15}, /* C57 */
{TS_GPIO_I, 0}, /* C58 */
{TS_GPIO_I, 13}, /* C59 */
{TS_GPIO_I, 7}, /* C60 */
};
BUILD_ASSERT(ARRAY_SIZE(col_pins) == COL_COUNT);
static const char *get_version(void)
{
/* TODO: refine this when we have RW */
return version_data.version;
}
static void low_power(void)
{
touch_scan_enable_interrupt();
master_slave_enable_interrupt();
CPU_SCB_SYSCTRL |= 0x4;
asm volatile("wfi");
CPU_SCB_SYSCTRL &= ~0x4;
hardware_clock_init();
touch_scan_disable_interrupt();
master_slave_disable_interrupt();
master_slave_wake_other();
/* Wait for the other chip to wake */
udelay(2 * MSEC);
master_slave_sync(5);
}
int main(void)
{
int i = 0;
hardware_init();
touch_scan_init();
debug_printf("%s starting...\n", get_version());
master_slave_init();
/* We want master SPI_NSS low and slave SPI_NSS high */
STM32_GPIO_BSRR(GPIO_A) = (1 << (1 + 16)) | (1 << 6);
master_slave_sync(10);
if (master_slave_is_master())
spi_master_init();
else
spi_slave_init();
master_slave_sync(100);
debug_printf("Touch to start...");
low_power();
debug_printf("\n");
while (1) {
i++;
task_wait_event(SECOND);
if (master_slave_is_master()) {
debug_printf("Hello x 50...");
if (spi_hello_test(50) == EC_SUCCESS)
debug_printf("Passed\n");
else
debug_printf("Failed\n");
task_wait_event(SECOND);
debug_printf("Scan...");
if (touch_scan_full_matrix() == EC_SUCCESS)
debug_printf("Passed\n");
else {
debug_printf("Failed\n");
task_wait_event(-1);
}
}
}
}

52
board/keyborg/board.h
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@@ -1,52 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Keyborg board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* Optional features */
#define CONFIG_DEBUG_PRINTF
#define CONFIG_KEYBORG_FAST_SCAN
#define CONFIG_KEYBORG_SPI_FULL_PACKET
#undef CONFIG_ADC
#undef CONFIG_COMMON_GPIO
#undef CONFIG_COMMON_PANIC_OUTPUT
#undef CONFIG_COMMON_RUNTIME
#undef CONFIG_COMMON_TIMER
#undef CONFIG_CONSOLE_CMDHELP
#undef CONFIG_DEBUG_EXCEPTIONS
#undef CONFIG_DEBUG_STACK_OVERFLOW
#undef CONFIG_FLASH
#undef CONFIG_FMAP
#undef CONFIG_LID_SWITCH
#undef CONFIG_TASK_PROFILING
#undef CONFIG_WATCHDOG_HELP
/* How the touch data is stored and printed */
#define CONFIG_ENCODE_SEGMENT
#undef CONFIG_ENCODE_RAW
#undef CONFIG_ENCODE_DUMP_PYTHON
#ifndef __ASSEMBLER__
enum gpio_signal;
/* Initialize all useful registers */
void hardware_init(void);
/* Re-initialize clock */
void hardware_clock_init(void);
/* On the master, reboot both chips. On the slave, reboot itself. */
void system_reboot(void);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

15
board/keyborg/build.mk
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@@ -1,15 +0,0 @@
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32TS60
CHIP:=stm32
CHIP_FAMILY:=stm32f
CHIP_VARIANT:=stm32ts60
board-y=board.o hardware.o runtime.o master_slave.o spi_comm.o touch_scan.o
board-$(CONFIG_ENCODE_SEGMENT)+=encode_segment.o
board-$(CONFIG_ENCODE_RAW)+=encode_raw.o
board-$(CONFIG_DEBUG_PRINTF)+=debug.o

49
board/keyborg/debug.c
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@@ -1,49 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* GPIO UART debug printf */
#include "common.h"
#include "printf.h"
#include "registers.h"
#include "timer.h"
#include "util.h"
#define BAUD 38400
#define BIT_PERIOD (1000000 / BAUD)
int debug_txchar(void *context, int c)
{
int i;
timestamp_t st;
int32_t d;
if (c == '\n')
debug_txchar(context, '\r');
c = (c << 1) | (1 << 9);
st = get_time();
for (i = 0; i < 10; ++i) {
STM32_GPIO_BSRR(GPIO_A) = 1 << ((c & 1) ? 15 : 31);
d = (int32_t)st.le.lo + BIT_PERIOD * (i + 1) - get_time().le.lo;
if (d > 0)
udelay(d);
c >>= 1;
}
return 0;
}
void debug_printf(const char *format, ...)
{
va_list args;
va_start(args, format);
vfnprintf(debug_txchar, NULL, format, args);
va_end(args);
}
void panic(const char *msg)
{
}

16
board/keyborg/debug.h
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@@ -1,16 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* GPIO UART debug printf */
#ifndef __BOARD_KEYBORG_DEBUG_H
#define __BOARD_KEYBORG_DEBUG_H
#ifdef CONFIG_DEBUG_PRINTF
void debug_printf(const char *format, ...);
#else
#define debug_printf(...)
#endif
#endif /* __BOARD_KEYBORG_DEBUG_H */

15
board/keyborg/ec.irqlist
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@@ -1,15 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled IRQ. To enable an IRQ, use ENABLE_IRQ(irq_num). Any
* IRQ that is not listed here is disabled.
*/
ENABLE_IRQ(STM32_IRQ_EXTI0)
ENABLE_IRQ(STM32_IRQ_EXTI1)
ENABLE_IRQ(STM32_IRQ_EXTI2)
ENABLE_IRQ(STM32_IRQ_EXTI3)
ENABLE_IRQ(STM32_IRQ_TIM2)

19
board/keyborg/ec.tasklist
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@@ -1,19 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST

20
board/keyborg/encode.h
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@@ -1,20 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Touch data encoding/decoding */
#ifndef __KEYBORG_ENCODE_H
#define __KEYBORG_ENCODE_H
/* Start encoding a new frame */
void encode_reset(void);
/* Encode a single column */
void encode_add_column(const uint8_t *dptr);
/* Decode and print the encoded frame to console */
void encode_dump_matrix(void);
#endif /* __KEYBORG_ENCODE_H */

58
board/keyborg/encode_raw.c
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@@ -1,58 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Raw touch data recording */
#include "common.h"
#include "debug.h"
#include "touch_scan.h"
#include "util.h"
#define ENC_COL_COUNT 70
static uint8_t encoded[ENC_COL_COUNT][ROW_COUNT * 2];
static int encoded_col;
void encode_reset(void)
{
encoded_col = 0;
}
void encode_add_column(const uint8_t *dptr)
{
if (encoded_col >= ENC_COL_COUNT)
return;
memcpy(encoded[encoded_col], dptr, ROW_COUNT * 2);
encoded_col++;
}
void encode_dump_matrix(void)
{
int row, col;
#ifdef CONFIG_ENCODE_DUMP_PYTHON
debug_printf("heat_map = [");
for (row = 0; row < ROW_COUNT * 2; ++row) {
debug_printf("[");
for (col = 0; col < encoded_col; ++col) {
if (encoded[col][row] < THRESHOLD)
debug_printf("0,");
else
debug_printf("%d,", encoded[col][row]);
}
debug_printf("],\n");
}
debug_printf("]\n");
#else
for (row = 0; row < ROW_COUNT * 2; ++row) {
for (col = 0; col < encoded_col; ++col) {
if (encoded[col][row] < THRESHOLD)
debug_printf(" - ");
else
debug_printf("%3d ", encoded[col][row]);
}
debug_printf("\n");
}
#endif
}

144
board/keyborg/encode_segment.c
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@@ -1,144 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Touch data encoding/decoding */
/*
* This removes the "whitespace" (i.e. cells below the threshold) and
* group the remaining active cells into "segments". By only storing
* the segments, we can fit a single frame in RAM in most cases.
*/
#include "common.h"
#include "debug.h"
#include "touch_scan.h"
#include "util.h"
#define BUF_SIZE 6000
static uint8_t encoded[BUF_SIZE];
static int encoded_size;
void encode_reset(void)
{
/* Just clear the encoded data */
encoded_size = 0;
}
void encode_add_column(const uint8_t *dptr)
{
uint8_t *seg_count_ptr;
int p, p_start;
uint8_t *eptr = encoded + encoded_size, *e_seg_size;
seg_count_ptr = eptr;
eptr++;
*seg_count_ptr = 0;
p = 0;
while (p < ROW_COUNT * 2) {
if (dptr[p] < THRESHOLD) {
++p;
continue;
}
/* Give up on overflow */
if (eptr + 2 >= encoded + BUF_SIZE)
return;
/* Save current position */
*(eptr++) = p;
/* Leave a byte for storing segment size */
e_seg_size = eptr;
eptr++;
/* Record segment starting point */
p_start = p;
/* Save the segment */
while (p < ROW_COUNT * 2 && dptr[p] >= THRESHOLD) {
if (eptr >= encoded + BUF_SIZE)
return;
*(eptr++) = dptr[p++];
}
/* Fill in the segment size now that we know it */
*e_seg_size = p - p_start;
(*seg_count_ptr)++;
}
/* Update encoded data size now that we're sure it fits */
encoded_size = eptr - encoded;
}
void encode_dump_matrix(void)
{
uint8_t *dptr;
int row, col;
int seg_count;
int seg;
int seg_end;
debug_printf("Encoded size = %d\n", encoded_size);
#ifdef CONFIG_ENCODE_DUMP_PYTHON
debug_printf("heat_map = [");
dptr = encoded;
for (col = 0; col < COL_COUNT * 2; ++col) {
debug_printf("[");
if (dptr >= encoded + encoded_size) {
debug_printf("0] * %d,\n", ROW_COUNT * 2);
continue;
}
seg_count = *(dptr++);
row = 0;
for (seg = 0; seg < seg_count; ++seg) {
if (row < *dptr) {
debug_printf("] + [0] * %d + [", *dptr - row);
row = *dptr;
}
dptr++;
seg_end = *dptr + row;
dptr++;
for (; row < seg_end; ++row, ++dptr)
debug_printf("%d,", *dptr);
}
if (row < ROW_COUNT * 2)
debug_printf("] + [0] * %d,\n", ROW_COUNT * 2 - row);
else
debug_printf("],\n");
}
debug_printf("]\n");
#else
dptr = encoded;
for (col = 0; col < COL_COUNT * 2; ++col) {
if (dptr >= encoded + encoded_size) {
for (row = 0; row < ROW_COUNT * 2; ++row)
debug_printf(" - ");
debug_printf("\n");
continue;
}
seg_count = *(dptr++);
row = 0;
for (seg = 0; seg < seg_count; ++seg) {
while (row < *dptr) {
debug_printf(" - ");
row++;
}
dptr++;
seg_end = *dptr + row;
dptr++;
for (; row < seg_end; ++row, ++dptr)
debug_printf("%3d ", *dptr);
}
while (row < ROW_COUNT * 2) {
debug_printf(" - ");
row++;
}
debug_printf("\n");
}
#endif
}

192
board/keyborg/hardware.c
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@@ -1,192 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Hardware initialization and common functions */
#include "common.h"
#include "cpu.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
#include "touch_scan.h"
#include "util.h"
void hardware_clock_init(void)
{
/* Turn on HSE */
if (!(STM32_RCC_CR & (1 << 17))) {
/* Enable HSE */
STM32_RCC_CR |= (1 << 18) | (1 << 16);
/* Wait for HSE to be ready */
while (!(STM32_RCC_CR & (1 << 17)))
;
}
/* PLLSRC = HSE/2 = 8MHz, PLLMUL = x6 = 48MHz */
STM32_RCC_CFGR = 0x00534000;
/* Enable PLL */
STM32_RCC_CR |= 1 << 24;
/* Wait for PLL to be ready */
while (!(STM32_RCC_CR & (1 << 25)))
;
/* switch SYSCLK to PLL */
STM32_RCC_CFGR = 0x00534002;
/* wait until the PLL is the clock source */
while ((STM32_RCC_CFGR & 0xc) != 0x8)
;
}
static void power_init(void)
{
/* enable ADC1, ADC2, PMSE, SPI1, GPA-GPI, AFIO */
STM32_RCC_APB2ENR = 0x0000f7fd;
/* enable TIM2, TIM3, PWR */
STM32_RCC_APB1ENR = 0x10000003;
/* enable DMA, SRAM */
STM32_RCC_AHBENR = 0x000005;
}
/* GPIO setting helpers */
#define OUT(n) (0x1 << ((n & 0x7) * 4))
#define OUT50(n) (0x3 << ((n & 0x7) * 4))
#define ANALOG(n) (0x0)
#define FLOAT(n) (0x4 << ((n & 0x7) * 4))
#define GP_OD(n) (0x5 << ((n & 0x7) * 4))
#define AF_PP(n) (0x9 << ((n & 0x7) * 4))
#define AF_OD(n) (0xd << ((n & 0x7) * 4))
#define LOW(n) (1 << (n + 16))
#define HIGH(n) (1 << n)
#define INT(n) (1 << n)
static void pins_init(void)
{
/*
* Disable JTAG and SWD. We want JTDI for UART Tx and SWD pins for
* touch scan.
*/
STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24))
| (4 << 24);
/*
* Initial pin usage:
* PA0: SPI_NSS - INPUT/INT_FALLING
* PA1: N_CHG - INPUT
* PA3: SPI_CLK - INPUT
* PA4: SPI_MISO - INPUT
* PA6: CS1 - OUTPUT/HIGH
* PA7: SPI_MOSI - INPUT
* PA9: USB_PU - OUTPUT/LOW
* PA15: UART TX - OUTPUT/HIGH
* PI1: SYNC1 - OUTPUT/LOW
* PI2: SYNC2 - OUTPUT/LOW
*/
STM32_GPIO_CRL(GPIO_A) = FLOAT(0) | FLOAT(1) | FLOAT(3) | FLOAT(4) |
OUT(6) | FLOAT(7);
STM32_GPIO_CRH(GPIO_A) = OUT(9) | OUT(15);
STM32_GPIO_BSRR(GPIO_A) = LOW(1) | HIGH(6) | LOW(9) | HIGH(15);
STM32_EXTI_FTSR |= INT(0);
STM32_GPIO_CRL(GPIO_I) = OUT(1) | OUT(2);
STM32_GPIO_BSRR(GPIO_I) = LOW(1) | LOW(2);
}
static void adc_init(void)
{
int id;
for (id = 0; id < 2; ++id) {
/* Enable ADC clock */
STM32_RCC_APB2ENR |= (1 << (14 + id));
/* Power on ADC if it's off */
if (!(STM32_ADC_CR2(id) & (1 << 0))) {
/* Power on ADC module */
STM32_ADC_CR2(id) |= (1 << 0); /* ADON */
/* Reset calibration */
STM32_ADC_CR2(id) |= (1 << 3); /* RSTCAL */
while (STM32_ADC_CR2(id) & (1 << 3))
;
/* A/D Calibrate */
STM32_ADC_CR2(id) |= (1 << 2); /* CAL */
while (STM32_ADC_CR2(id) & (1 << 2))
;
}
/* Set right alignment */
STM32_ADC_CR2(id) &= ~(1 << 11);
/* Set sampling time */
STM32_ADC_SMPR2(id) = ADC_SMPR_VAL;
/* Select AIN0 */
STM32_ADC_SQR3(id) &= ~0x1f;
/* Disable DMA */
STM32_ADC_CR2(id) &= ~(1 << 8);
/* Disable scan mode */
STM32_ADC_CR1(id) &= ~(1 << 8);
}
}
static void timers_init(void)
{
STM32_TIM_CR1(3) = 0x0004; /* MSB */
STM32_TIM_CR1(2) = 0x0004; /* LSB */
STM32_TIM_CR2(3) = 0x0000;
STM32_TIM_CR2(2) = 0x0020;
STM32_TIM_SMCR(3) = 0x0007 | (1 << 4);
STM32_TIM_SMCR(2) = 0x0000;
STM32_TIM_ARR(3) = 0xffff;
STM32_TIM_ARR(2) = 0xffff;
STM32_TIM_PSC(3) = 0;
STM32_TIM_PSC(2) = CPU_CLOCK / 1000000 - 1;
STM32_TIM_EGR(3) = 0x0001;
STM32_TIM_EGR(2) = 0x0001;
STM32_TIM_DIER(3) = 0x0001;
STM32_TIM_DIER(2) = 0x0000;
STM32_TIM_CR1(3) |= 1;
STM32_TIM_CR1(2) |= 1;
STM32_TIM_CNT(3) = 0;
STM32_TIM_CNT(2) = 0;
task_enable_irq(STM32_IRQ_TIM3);
task_enable_irq(STM32_IRQ_TIM2);
}
static void irq_init(void)
{
/* clear all pending interrupts */
CPU_NVIC_UNPEND(0) = 0xffffffff;
/* enable global interrupts */
asm("cpsie i");
}
static void pmse_init(void)
{
/* Use 10K-ohm pull down */
STM32_PMSE_CR |= (1 << 13);
}
void hardware_init(void)
{
power_init();
hardware_clock_init();
pins_init();
timers_init();
adc_init();
irq_init();
pmse_init();
}

192
board/keyborg/master_slave.c
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Master/slave identification */
#include "config.h"
#include "debug.h"
#include "master_slave.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#define SYNC1 (1 << 1) /* PI1 */
#define SYNC2 (1 << 2) /* PI2 */
static int is_master = -1;
int master_slave_is_master(void)
{
return is_master;
}
static int wait_sync_signal(int mask, int v, int timeout_ms)
{
uint32_t start = get_time().le.lo;
while ((!!(STM32_GPIO_IDR(GPIO_I) & mask)) != v) {
if ((get_time().le.lo - start) >= timeout_ms * MSEC)
return EC_ERROR_TIMEOUT;
}
return EC_SUCCESS;
}
int master_slave_sync_impl(const char *filename, int line, int timeout_ms)
{
int err = EC_SUCCESS;
if (is_master) {
STM32_GPIO_BSRR(GPIO_I) = SYNC1 << 0;
if (wait_sync_signal(SYNC2, 1, timeout_ms))
err = EC_ERROR_TIMEOUT;
STM32_GPIO_BSRR(GPIO_I) = SYNC1 << 16;
if (wait_sync_signal(SYNC2, 0, 5))
err = EC_ERROR_TIMEOUT;
} else {
if (wait_sync_signal(SYNC1, 1, timeout_ms))
err = EC_ERROR_TIMEOUT;
STM32_GPIO_BSRR(GPIO_I) = SYNC2 << 0;
if (wait_sync_signal(SYNC1, 0, 5))
err = EC_ERROR_TIMEOUT;
STM32_GPIO_BSRR(GPIO_I) = SYNC2 << 16;
}
if (err != EC_SUCCESS)
debug_printf("Sync failed at %s:%d\n", filename, line);
return err;
}
void master_slave_enable_interrupt(void)
{
if (is_master) {
/* Interrupt on EXTI2 on port I */
STM32_EXTI_RTSR |= 1 << 2;
STM32_AFIO_EXTICR(0) = (STM32_AFIO_EXTICR(0) & ~0xf00) |
(8 << 8);
STM32_EXTI_IMR |= 1 << 2;
task_clear_pending_irq(STM32_IRQ_EXTI2);
task_enable_irq(STM32_IRQ_EXTI2);
} else {
/* Interrupt on EXTI1 on port I */
STM32_EXTI_RTSR |= 1 << 1;
STM32_AFIO_EXTICR(0) = (STM32_AFIO_EXTICR(0) & ~0xf0) |
(8 << 4);
STM32_EXTI_IMR |= 1 << 1;
task_clear_pending_irq(STM32_IRQ_EXTI1);
task_enable_irq(STM32_IRQ_EXTI1);
}
}
void master_slave_disable_interrupt(void)
{
if (is_master)
task_disable_irq(STM32_IRQ_EXTI2);
else
task_disable_irq(STM32_IRQ_EXTI1);
}
void master_slave_wake_other(void)
{
if (is_master) {
STM32_GPIO_BSRR(GPIO_I) = SYNC1 << 0;
udelay(MSEC);
STM32_GPIO_BSRR(GPIO_I) = SYNC1 << 16;
} else {
STM32_GPIO_BSRR(GPIO_I) = SYNC2 << 0;
udelay(MSEC);
STM32_GPIO_BSRR(GPIO_I) = SYNC2 << 16;
}
}
void master_slave_interrupt(void)
{
STM32_EXTI_PR = STM32_EXTI_PR;
}
DECLARE_IRQ(STM32_IRQ_EXTI1, master_slave_interrupt, 1);
DECLARE_IRQ(STM32_IRQ_EXTI2, master_slave_interrupt, 1);
static int master_handshake(void)
{
uint32_t val;
int err;
/* SYNC2 is the sync signal from the slave. Set it to input. */
val = STM32_GPIO_CRL(GPIO_I);
val &= ~0x00000f00;
val |= 0x00000400;
STM32_GPIO_CRL(GPIO_I) = val;
err = master_slave_sync(1000);
err |= master_slave_sync(20);
err |= master_slave_sync(20);
return err;
}
static int slave_handshake(void)
{
uint32_t val;
int err;
/*
* N_CHG is used to drive SPI_NSS on the master. Set it to
* output low.
*/
val = STM32_GPIO_CRL(GPIO_A);
val &= ~0x000000f0;
val |= 0x00000010;
STM32_GPIO_CRL(GPIO_A) = val;
STM32_GPIO_BSRR(GPIO_A) = 1 << (1 + 16);
/* SYNC1 is the sync signal from the master. Set it to input. */
val = STM32_GPIO_CRL(GPIO_I);
val &= ~0x000000f0;
val |= 0x00000040;
STM32_GPIO_CRL(GPIO_I) = val;
err = master_slave_sync(1000);
err |= master_slave_sync(20);
err |= master_slave_sync(20);
return err;
}
static void master_slave_check(void)
{
/*
* Master slave identity check:
* - Master has USB_PU connected to N_CHG through 1.5K
* resistor. USB_PU is initially low, so N_CHG is low.
* - Slave has N_CHG connected to master NSS with a 20K
* pull-up. Master NSS is initially Hi-Z, so N_CHG is
* high.
*/
if (STM32_GPIO_IDR(GPIO_A) & (1 << 1) /* N_CHG */) {
debug_printf("I'm slave\n");
is_master = 0;
} else {
debug_printf("I'm master\n");
is_master = 1;
}
}
int master_slave_init(void)
{
int handshake_err;
master_slave_check();
if (is_master)
handshake_err = master_handshake();
else
handshake_err = slave_handshake();
if (handshake_err != EC_SUCCESS)
debug_printf("handshake error\n");
else
debug_printf("handshake done\n");
return handshake_err;
}

49
board/keyborg/master_slave.h
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@@ -1,49 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Master/slave identification */
#ifndef __BOARD_KEYBORG_MASTER_SLAVE_H
#define __BOARD_KEYBORG_MASTER_SLAVE_H
/**
* Get the identity of this chip.
*
* @return 1 if master; otherwise, 0.
*/
int master_slave_is_master(void);
/**
* Synchronize with the other chip. The other chip must also call this
* function to synchronize.
*
* @param timeout_ms Timeout value in millisecond. If the other chip
* doesn't synchronize within this time, the sync
* call fails.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
#define master_slave_sync(timeout_ms) \
master_slave_sync_impl(__FILE__, __LINE__, timeout_ms)
int master_slave_sync_impl(const char *filename, int line, int timeout_ms);
/**
* Enable/disable master-slave interrupt. Master-slave interrupt is
* implemented using SYNC1/SYNC2 signal, so this is assuming the master
* and the slave are in sync waiting for interrupt.
*/
void master_slave_enable_interrupt(void);
void master_slave_disable_interrupt(void);
/* Interrupt the other chip with a 1-ms pulse. */
void master_slave_wake_other(void);
/**
* Identify this chip and shake hands with the other chip.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int master_slave_init(void);
#endif /* __BOARD_KEYBORG_MASTER_SLAVE_H */

143
board/keyborg/runtime.c
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@@ -1,143 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* tiny substitute of the runtime layer */
#include "common.h"
#include "cpu.h"
#include "debug.h"
#include "master_slave.h"
#include "registers.h"
#include "task.h"
#include "timer.h"
#include "util.h"
volatile uint32_t last_event;
static uint32_t last_deadline;
static uint8_t need_wfi;
timestamp_t get_time(void)
{
timestamp_t t;
uint32_t hi, lo;
do {
hi = STM32_TIM_CNT(3);
lo = STM32_TIM_CNT(2);
} while (hi != STM32_TIM_CNT(3));
t.le.lo = (hi << 16) | lo;
t.le.hi = 0;
return t;
}
void udelay(unsigned us)
{
unsigned t0 = get_time().le.lo;
while ((get_time().le.lo - t0) < us)
;
}
void task_enable_irq(int irq)
{
CPU_NVIC_EN(0) = 1 << irq;
}
void task_disable_irq(int irq)
{
CPU_NVIC_DIS(0) = 1 << irq;
}
void task_clear_pending_irq(int irq)
{
CPU_NVIC_UNPEND(0) = 1 << irq;
}
uint32_t task_set_event(task_id_t tskid, uint32_t event, int wait)
{
last_event = event;
return 0;
}
void tim2_interrupt(void)
{
if (STM32_TIM_CNT(3) == last_deadline >> 16) {
STM32_TIM_DIER(2) = 0;
task_clear_pending_irq(STM32_IRQ_TIM2);
last_event = TASK_EVENT_TIMER;
need_wfi = 0;
} else {
need_wfi = 1;
}
}
DECLARE_IRQ(STM32_IRQ_TIM2, tim2_interrupt, 1);
void __hw_clock_event_set(uint32_t deadline)
{
last_deadline = deadline;
STM32_TIM_CCR1(2) = deadline & 0xffff;
STM32_TIM_SR(2) = ~2;
STM32_TIM_DIER(2) |= 2;
}
uint32_t task_wait_event(int timeout_us)
{
uint32_t evt;
/* the event already happened */
if (last_event || !timeout_us) {
evt = last_event;
last_event = 0;
return evt;
}
/* set timeout on timer */
if (timeout_us > 0)
__hw_clock_event_set(get_time().le.lo + timeout_us);
do {
/* sleep until next interrupt */
asm volatile("wfi");
} while (need_wfi);
STM32_TIM_DIER(2) = 0; /* disable match interrupt */
evt = last_event;
last_event = 0;
return evt;
}
void system_reboot(void)
{
if (master_slave_is_master()) {
/* Ask the slave to reboot as well */
STM32_GPIO_BSRR(GPIO_A) = 1 << (6 + 16);
udelay(10 * MSEC); /* The slave reboots in 5 ms */
}
/* Ask the watchdog to trigger a hard reboot */
STM32_IWDG_KR = 0x5555;
STM32_IWDG_RLR = 0x1;
STM32_IWDG_KR = 0xcccc;
/* wait for the watchdog */
while (1)
;
}
/* Unhandled exception panic */
void exception_panic(void)
{
debug_printf("PANIC\n");
system_reboot();
}
/* --- stubs --- */
void __hw_timer_enable_clock(int n, int enable)
{ /* Done in hardware init */ }
void usleep(unsigned us)
{ /* Used only as a workaround */ }

491
board/keyborg/spi_comm.c
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@@ -1,491 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Stantum board-specific SPI module */
#include "common.h"
#include "debug.h"
#include "dma.h"
#include "master_slave.h"
#include "registers.h"
#include "spi_comm.h"
#include "task.h"
#include "timer.h"
#include "touch_scan.h"
#include "util.h"
#define DUMMY_DATA 0xdd
/* DMA channel option */
static const struct dma_option dma_tx_option = {
STM32_DMAC_SPI1_TX, (void *)&STM32_SPI1_REGS->dr,
STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT
};
static const struct dma_option dma_rx_option = {
STM32_DMAC_SPI1_RX, (void *)&STM32_SPI1_REGS->dr,
STM32_DMA_CCR_MSIZE_8_BIT | STM32_DMA_CCR_PSIZE_16_BIT
};
static uint8_t out_msg[SPI_PACKET_MAX_SIZE + 2];
static uint8_t in_msg[SPI_PACKET_MAX_SIZE];
static stm32_spi_regs_t * const spi = STM32_SPI1_REGS;
static inline int wait_for_signal(uint32_t port, uint32_t mask,
int value, int timeout_us)
{
uint32_t start = get_time().le.lo;
while ((get_time().le.lo - start) < timeout_us) {
if ((!!(STM32_GPIO_IDR(port) & mask)) == value)
return EC_SUCCESS;
}
return EC_ERROR_TIMEOUT;
}
static volatile uint8_t slave_ready = 1;
static inline int wait_for_slave_ready(int timeout_us)
{
uint32_t start = get_time().le.lo;
while ((get_time().le.lo - start) < timeout_us) {
if (slave_ready) {
slave_ready = 0; /* Clear for the next event */
return EC_SUCCESS;
}
}
return EC_ERROR_TIMEOUT;
}
/*****************************************************************************/
/* Master */
void spi_master_init(void)
{
/*
* CLK: AFIO Push-pull
* MISO: Input
* MOSI: AFIO Push-pull
*/
STM32_GPIO_CRL(GPIO_A) = (STM32_GPIO_CRL(GPIO_A) & 0x0ff00fff) |
0xb004b000;
/* Set BR in CR1 */
spi->cr1 |= STM32_SPI_CR1_BR_DIV4R;
/* Set CPOL and CPHA */
/* Use default: 0, 0 */
/* Set DFF to 8-bit */
/* Use default: 8-bit */
/* Configure LSBFIRST */
/* Use default: MSB first */
/* Set SSOE */
/* Use default: software control */
/* Enable TX and RX DMA */
spi->cr2 |= STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN;
/* Set SSM and SSI */
spi->cr1 |= STM32_SPI_CR1_SSM | STM32_SPI_CR1_SSI;
/* Enable CRC */
spi->cr1 |= STM32_SPI_CR1_CRCEN;
/* Set MSTR and SPE */
spi->cr1 |= STM32_SPI_CR1_MSTR | STM32_SPI_CR1_SPE;
/* Enable interrupt on PA0 (GPIO_SPI_NSS) */
STM32_AFIO_EXTICR(0) &= ~0xF;
STM32_EXTI_IMR |= (1 << 0);
task_clear_pending_irq(STM32_IRQ_EXTI0);
task_enable_irq(STM32_IRQ_EXTI0);
}
static int spi_master_read_write_byte(uint8_t *in_buf, uint8_t *out_buf, int sz)
{
int ret;
dma_start_rx(&dma_rx_option, sz, in_buf);
dma_prepare_tx(&dma_tx_option, sz, out_buf);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
ret = dma_wait(STM32_DMAC_SPI1_TX);
ret |= dma_wait(STM32_DMAC_SPI1_RX);
dma_disable(STM32_DMAC_SPI1_TX);
dma_disable(STM32_DMAC_SPI1_RX);
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
return ret;
}
int spi_master_send_command(struct spi_comm_packet *cmd)
{
int ret;
if (cmd->size + 3 > SPI_PACKET_MAX_SIZE)
return EC_ERROR_OVERFLOW;
/* Wait for SPI_NSS to go low */
if (wait_for_signal(GPIO_A, 1 << 0, 0, 10 * MSEC))
return EC_ERROR_TIMEOUT;
/* Set CS1 (slave SPI_NSS) to low */
STM32_GPIO_BSRR(GPIO_A) = 1 << (6 + 16);
/* Wait for the slave to acknowledge */
master_slave_sync(5);
/* Clock out the packet size. */
spi->dr = cmd->size;
while (!(spi->sr & STM32_SPI_SR_RXNE))
;
ret = spi->dr;
/* Wait for the slave to acknowledge */
master_slave_sync(5);
/* Clock out command. Don't care about input. */
ret = spi_master_read_write_byte(in_msg, ((uint8_t *)cmd) + 1,
cmd->size + SPI_PACKET_HEADER_SIZE - 1);
return ret;
}
int spi_master_wait_response_async(void)
{
wait_for_slave_ready(100 * MSEC);
if (wait_for_signal(GPIO_A, 1 << 0, 1, 40 * MSEC))
goto err_wait_resp_async;
/* Discard potential garbage in SPI DR */
if (spi->sr & STM32_SPI_SR_RXNE)
in_msg[0] = spi->dr;
#ifdef CONFIG_KEYBORG_SPI_FULL_PACKET
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
dma_start_rx(&dma_rx_option, SPI_PACKET_MAX_SIZE, in_msg);
dma_prepare_tx(&dma_tx_option, SPI_PACKET_MAX_SIZE, out_msg);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
#else
/* Get the packet size */
spi->dr = DUMMY_DATA;
while (!(spi->sr & STM32_SPI_SR_RXNE))
;
in_msg[0] = spi->dr;
master_slave_sync(5);
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
/* Get the rest of the packet*/
dma_start_rx(&dma_rx_option,
in_msg[0] + SPI_PACKET_HEADER_SIZE - 1,
in_msg + 1);
dma_prepare_tx(&dma_tx_option,
in_msg[0] + SPI_PACKET_HEADER_SIZE - 1,
out_msg);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
#endif
return EC_SUCCESS;
err_wait_resp_async:
/* Set CS1 (slave SPI_NSS) to high */
STM32_GPIO_BSRR(GPIO_A) = 1 << 6;
return EC_ERROR_TIMEOUT;
}
const struct spi_comm_packet *spi_master_wait_response_done(void)
{
const struct spi_comm_packet *resp =
(const struct spi_comm_packet *)in_msg;
if (dma_wait(STM32_DMAC_SPI1_TX) || dma_wait(STM32_DMAC_SPI1_RX)) {
debug_printf("SPI: Incomplete response\n");
goto err_wait_response_done;
}
if (spi->sr & STM32_SPI_SR_CRCERR) {
debug_printf("SPI: CRC mismatch\n");
goto err_wait_response_done;
}
if (resp->cmd_sts != EC_SUCCESS) {
debug_printf("SPI: Slave error\n");
goto err_wait_response_done;
}
exit_wait_response_done:
dma_disable(STM32_DMAC_SPI1_TX);
dma_disable(STM32_DMAC_SPI1_RX);
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_RX);
/* Set CS1 (slave SPI_NSS) to high */
STM32_GPIO_BSRR(GPIO_A) = 1 << 6;
return resp;
err_wait_response_done:
resp = NULL;
goto exit_wait_response_done;
}
const struct spi_comm_packet *spi_master_wait_response(void)
{
if (spi_master_wait_response_async() != EC_SUCCESS)
return NULL;
return spi_master_wait_response_done();
}
static uint32_t myrnd(void)
{
static uint32_t last = 0x1357;
return last = (last * 8001 + 1);
}
int spi_hello_test(int iteration)
{
int i, j, xv, sz;
struct spi_comm_packet *cmd = (struct spi_comm_packet *)out_msg;
const struct spi_comm_packet *resp;
for (i = 0; i < iteration; ++i) {
xv = myrnd() & 0xff;
cmd->cmd_sts = TS_CMD_HELLO;
sz = myrnd() % (sizeof(out_msg) - 10) + 1;
cmd->size = sz + 2;
cmd->data[0] = sz;
cmd->data[1] = xv;
for (j = 0; j < sz; ++j)
cmd->data[j + 2] = myrnd() & 0xff;
if (spi_master_send_command(cmd))
return EC_ERROR_UNKNOWN;
resp = spi_master_wait_response();
if (resp == NULL || resp->size != sz)
return EC_ERROR_UNKNOWN;
for (j = 0; j < sz; ++j)
if (cmd->data[j + 2] != resp->data[j])
return EC_ERROR_UNKNOWN;
resp = spi_master_wait_response();
if (resp == NULL || resp->size != sz)
return EC_ERROR_UNKNOWN;
for (j = 0; j < sz; ++j)
if ((cmd->data[j + 2] ^ xv) != resp->data[j])
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
/*****************************************************************************/
/* Slave */
void spi_slave_init(void)
{
/*
* MISO: AFIO Push-pull
*/
STM32_GPIO_CRL(GPIO_A) = (STM32_GPIO_CRL(GPIO_A) & 0xfff0ffff) |
0x000b0000;
/* Set DFF to 8-bit (default) */
/* Set CPOL and CPHA (default) */
/* Configure LSBFIRST (default) */
/* Set SSM and clear SSI */
spi->cr1 |= STM32_SPI_CR1_SSM;
spi->cr1 &= ~STM32_SPI_CR1_SSI;
/* Enable RXNE interrupt */
spi->cr2 |= STM32_SPI_CR2_RXNEIE;
/*task_enable_irq(STM32_IRQ_SPI1);*/
/* Enable TX and RX DMA */
spi->cr2 |= STM32_SPI_CR2_TXDMAEN | STM32_SPI_CR2_RXDMAEN;
/* Clear MSTR */
spi->cr1 &= ~STM32_SPI_CR1_MSTR;
/* Enable CRC */
spi->cr1 |= STM32_SPI_CR1_CRCEN;
/* Set SPE */
spi->cr1 |= STM32_SPI_CR1_SPE;
/* Dummy byte to clock out when the next packet comes in */
spi->dr = DUMMY_DATA;
/* Enable interrupt on PA0 (GPIO_SPI_NSS) */
STM32_AFIO_EXTICR(0) &= ~0xF;
STM32_EXTI_IMR |= (1 << 0);
task_clear_pending_irq(STM32_IRQ_EXTI0);
task_enable_irq(STM32_IRQ_EXTI0);
}
int spi_slave_send_response(struct spi_comm_packet *resp)
{
int r;
r = spi_slave_send_response_async(resp);
r |= spi_slave_send_response_flush();
return r;
}
int spi_slave_send_response_async(struct spi_comm_packet *resp)
{
int size = resp->size + SPI_PACKET_HEADER_SIZE;
if (size > SPI_PACKET_MAX_SIZE)
return EC_ERROR_OVERFLOW;
if (out_msg != (uint8_t *)resp)
memcpy(out_msg, resp, size);
#ifdef CONFIG_KEYBORG_SPI_FULL_PACKET
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_prepare_tx(&dma_tx_option, SPI_PACKET_MAX_SIZE, out_msg);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
/* Set N_CHG (master SPI_NSS) to high */
STM32_GPIO_BSRR(GPIO_A) = 1 << 1;
#else
if (spi->sr & STM32_SPI_SR_RXNE)
in_msg[0] = spi->dr;
spi->dr = out_msg[0];
/* Set N_CHG (master SPI_NSS) to high */
STM32_GPIO_BSRR(GPIO_A) = 1 << 1;
while (!(spi->sr & STM32_SPI_SR_RXNE))
;
in_msg[0] = spi->dr;
dma_clear_isr(STM32_DMAC_SPI1_TX);
dma_prepare_tx(&dma_tx_option, size - 1, out_msg + 1);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
if (master_slave_sync(5) != EC_SUCCESS)
return EC_ERROR_UNKNOWN;
#endif
return EC_SUCCESS;
}
int spi_slave_send_response_flush(void)
{
int ret;
ret = dma_wait(STM32_DMAC_SPI1_TX);
dma_disable(STM32_DMAC_SPI1_TX);
dma_clear_isr(STM32_DMAC_SPI1_TX);
/* Set N_CHG (master SPI_NSS) to low */
STM32_GPIO_BSRR(GPIO_A) = 1 << (1 + 16);
return ret;
}
static void spi_slave_nack(void)
{
struct spi_comm_packet *resp = (struct spi_comm_packet *)out_msg;
resp->cmd_sts = EC_ERROR_UNKNOWN;
resp->size = 0;
spi_slave_send_response(resp);
}
static void spi_slave_hello_back(const struct spi_comm_packet *cmd)
{
struct spi_comm_packet *resp = (struct spi_comm_packet *)out_msg;
uint8_t buf[SPI_PACKET_MAX_SIZE];
int i, sz;
sz = cmd->data[0];
memcpy(buf, cmd->data, sz + 2);
resp->cmd_sts = EC_SUCCESS;
resp->size = sz;
for (i = 0; i < sz; ++i)
resp->data[i] = cmd->data[i + 2];
spi_slave_send_response(resp);
for (i = 0; i < sz; ++i)
resp->data[i] = buf[i + 2] ^ buf[1];
spi_slave_send_response(resp);
}
static void spi_nss_interrupt(void)
{
const struct spi_comm_packet *cmd =
(const struct spi_comm_packet *)in_msg;
if (master_slave_is_master()) {
slave_ready = 1;
return;
}
if (spi->sr & STM32_SPI_SR_RXNE)
in_msg[0] = spi->dr;
/*
* SPI_NSS is also used for the master to reboot the slave.
* If SPI_NSS goes low without a sync in time, reboots.
*/
if (master_slave_sync(5))
system_reboot();
/* Read in the packet size */
while (!(spi->sr & STM32_SPI_SR_RXNE))
;
in_msg[0] = spi->dr;
/* Read in the rest of the packet */
dma_clear_isr(STM32_DMAC_SPI1_RX);
dma_start_rx(&dma_rx_option, in_msg[0] + SPI_PACKET_HEADER_SIZE - 1,
in_msg + 1);
dma_prepare_tx(&dma_tx_option, in_msg[0] + SPI_PACKET_HEADER_SIZE - 1,
out_msg);
dma_go(dma_get_channel(STM32_DMAC_SPI1_TX));
master_slave_sync(5);
if (dma_wait(STM32_DMAC_SPI1_RX) != EC_SUCCESS) {
debug_printf("SPI: Incomplete packet\n");
spi_slave_nack();
return;
}
if (spi->sr & STM32_SPI_SR_CRCERR) {
debug_printf("SPI: CRC mismatch\n");
spi_slave_nack();
return;
}
if (cmd->cmd_sts == TS_CMD_HELLO)
spi_slave_hello_back(cmd);
else if (cmd->cmd_sts == TS_CMD_FULL_SCAN)
touch_scan_slave_start();
else
spi_slave_nack();
}
/* Interrupt handler for PA0 */
void spi_nss_interrupt_handler(void)
{
/* Clear the interrupt */
STM32_EXTI_PR = STM32_EXTI_PR;
/* SPI slave interrupt */
spi_nss_interrupt();
}
DECLARE_IRQ(STM32_IRQ_EXTI0, spi_nss_interrupt_handler, 1);

96
board/keyborg/spi_comm.h
View File

@@ -1,96 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#ifndef __BOARD_KEYBORG_SPI_COMM_H
#define __BOARD_KEYBORG_SPI_COMM_H
#define SPI_PACKET_MAX_SIZE 64
enum ts_command {
TS_CMD_HELLO = 0,
TS_CMD_FULL_SCAN,
};
struct spi_comm_packet {
uint8_t size;
uint8_t cmd_sts;
uint8_t data[0];
};
#define SPI_PACKET_HEADER_SIZE 2
/* Initialize SPI interface for the master chip */
void spi_master_init(void);
/* Initialize SPI interface for the slave chip */
void spi_slave_init(void);
/*
* Calculate checksum and send command packet to the slave.
*
* @param cmd Pointer to the command packet.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int spi_master_send_command(struct spi_comm_packet *cmd);
/*
* Wait for slave response and verify checksum.
*
* @return Pointer to the response packet, or NULL if any error.
*/
const struct spi_comm_packet *spi_master_wait_response(void);
/*
* Start receiving slave response, but don't wait for full transaction.
* The caller is responsible for calling spi_master_wait_response_done()
* to ensure the response is fully received.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int spi_master_wait_response_async(void);
/*
* Wait for slave response to complete.
*
* @return Pointer to the response packet, or NULL if any error.
*/
const struct spi_comm_packet *spi_master_wait_response_done(void);
/*
* Calculate checksum and send response packet to the master.
*
* @param resp Pointer to the response packet.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int spi_slave_send_response(struct spi_comm_packet *resp);
/*
* Start sending response to the master, but don't block. The caller is
* responsible for calling spi_slave_send_response_flush() to ensure
* the response is fully transmitted.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int spi_slave_send_response_async(struct spi_comm_packet *resp);
/*
* Wait until the last response is sent out.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int spi_slave_send_response_flush(void);
/*
* Perform random back-to-back hello test. Master only.
*
* @param iteration Number of hello messages to send.
*
* @return EC_SUCCESS, or non-zero if any error.
*/
int spi_hello_test(int iteration);
#endif /* __BOARD_KEYBORG_SPI_COMM_H */

414
board/keyborg/touch_scan.c
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@@ -1,414 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Touch scanning module */
#include "common.h"
#include "console.h"
#include "cpu.h"
#include "debug.h"
#include "dma.h"
#include "encode.h"
#include "gpio.h"
#include "hooks.h"
#include "master_slave.h"
#include "registers.h"
#include "spi_comm.h"
#include "task.h"
#include "timer.h"
#include "touch_scan.h"
#include "util.h"
#define TS_PIN_TO_CR(p) ((((p).port_id + 1) << 16) | (1 << (p).pin))
#define TS_GPIO_TO_BASE(p) (0x40010800 + (p) * 0x400)
static uint8_t buf[2][ROW_COUNT * 2];
#ifdef CONFIG_KEYBORG_FAST_SCAN
#define SCAN_BUF_SIZE (DIV_ROUND_UP(COL_COUNT * 2, 32) + 2)
#define GET_SCAN_NEEDED(x) (scan_needed[(x) / 32 + 1] & (1 << ((x) & 31)))
static uint32_t scan_needed[SCAN_BUF_SIZE];
#else
#define GET_SCAN_NEEDED(x) 1
#endif
#define SPAN_LENGTH (2 * COL_SPAN + 1)
#define SPAN_MASK ((1 << SPAN_LENGTH) - 1)
static uint32_t mccr_list[COL_COUNT];
static uint32_t mrcr_list[ROW_COUNT];
static void set_gpio(const struct ts_pin pin, enum pin_type type)
{
uint32_t addr, mode, mask;
uint32_t port = TS_GPIO_TO_BASE(pin.port_id);
uint32_t pmask = 1 << pin.pin;
if (pmask & 0xff) {
addr = port;
mode = pmask;
} else {
addr = port + 0x04;
mode = pmask >> 8;
}
mode = mode * mode * mode * mode * 0xf;
mask = REG32(addr) & ~mode;
if (type == PIN_COL) {
/* Alternate output open-drain */
mask |= 0xdddddddd & mode;
} else if (type == PIN_PD) {
mask |= 0x88888888 & mode;
STM32_GPIO_BSRR(port) = pmask << 16;
} else if (type == PIN_Z) {
mask |= 0x44444444 & mode;
} else if (type == PIN_ROW) {
/* Nothing for PIN_ROW. Already analog input. */
}
REG32(addr) = mask;
}
void touch_scan_init(void)
{
int i;
for (i = 0; i < ROW_COUNT; ++i) {
set_gpio(row_pins[i], PIN_ROW);
STM32_PMSE_PxPMR(row_pins[i].port_id) |= 1 << row_pins[i].pin;
}
for (i = 0; i < COL_COUNT; ++i)
set_gpio(col_pins[i], PIN_PD);
for (i = 0; i < ROW_COUNT; ++i)
mrcr_list[i] = TS_PIN_TO_CR(row_pins[i]);
for (i = 0; i < COL_COUNT; ++i)
mccr_list[i] = TS_PIN_TO_CR(col_pins[i]);
}
void touch_scan_enable_interrupt(void)
{
int i;
/* Set ALLROW and ALLCOL */
for (i = 0; i < ROW_COUNT; ++i)
set_gpio(row_pins[i], PIN_Z);
for (i = 0; i < COL_COUNT; ++i) {
set_gpio(col_pins[i], PIN_COL);
STM32_PMSE_PxPMR(col_pins[i].port_id) |= 1 << col_pins[i].pin;
}
STM32_PMSE_MCCR = (1 << 31) | (0 << 20);
STM32_PMSE_MRCR = 1 << 31;
/* Enable external interrupt. EXTI3 on port E. Rising edge */
STM32_EXTI_RTSR |= 1 << 3;
STM32_AFIO_EXTICR(0) = (STM32_AFIO_EXTICR(0) & ~0xf000) | (4 << 12);
STM32_EXTI_IMR |= 1 << 3;
task_clear_pending_irq(STM32_IRQ_EXTI3);
task_enable_irq(STM32_IRQ_EXTI3);
}
void touch_scan_disable_interrupt(void)
{
int i;
for (i = 0; i < ROW_COUNT; ++i)
set_gpio(row_pins[i], PIN_ROW);
for (i = 0; i < COL_COUNT; ++i) {
set_gpio(col_pins[i], PIN_PD);
STM32_PMSE_PxPMR(col_pins[i].port_id) &=
~(1 << col_pins[i].pin);
}
}
void touch_scan_interrupt(void)
{
STM32_EXTI_PR = STM32_EXTI_PR;
}
DECLARE_IRQ(STM32_IRQ_EXTI3, touch_scan_interrupt, 1);
static void discharge(void)
{
int i;
/*
* The value 20 is deducted from experiments.
* Somehow this needs to be in reverse order
*/
for (i = 20; i >= 0; --i)
STM32_PMSE_MRCR = mrcr_list[i];
}
static void start_adc_sample(int id, int wait_cycle)
{
/* Clear EOC and STRT bit */
STM32_ADC_SR(id) &= ~((1 << 1) | (1 << 4));
/* Start conversion */
STM32_ADC_CR2(id) |= (1 << 0);
/* Wait for conversion start */
while (!(STM32_ADC_SR(id) & (1 << 4)))
;
/* Each iteration takes 3 CPU cycles */
asm("1: subs %0, #1\n"
" bne 1b\n" :: "r"(wait_cycle / 3));
}
static inline uint8_t flush_adc(int id)
{
uint16_t v;
#if ADC_SMPL_CYCLE_2 < ADC_QUNTZ_CYCLE_2
while (!(STM32_ADC_SR(id) & (1 << 1)))
;
#endif
v = STM32_ADC_DR(id) >> ADC_WINDOW_POS;
if (v > 255)
v = 255;
return v;
}
static void enable_col(int idx, int enabled)
{
if (enabled) {
set_gpio(col_pins[idx], PIN_COL);
STM32_PMSE_PxPMR(col_pins[idx].port_id) |=
1 << col_pins[idx].pin;
} else {
set_gpio(col_pins[idx], PIN_PD);
STM32_PMSE_PxPMR(col_pins[idx].port_id) &=
~(1 << col_pins[idx].pin);
}
}
#ifdef CONFIG_KEYBORG_FAST_SCAN
static inline void set_scan_needed(int col)
{
uint8_t word = (col - COL_SPAN + 32) / 32;
uint8_t bit = (col - COL_SPAN + 32) & 31;
scan_needed[word] |= SPAN_MASK << bit;
if (bit + SPAN_LENGTH > 32)
scan_needed[word + 1] |= SPAN_MASK >> (32 - bit);
}
int fast_scan(uint32_t *data)
{
int col;
int chip_col = 0;
memset(data, 0, SCAN_BUF_SIZE * 4);
STM32_PMSE_MRCR = 1 << 31;
for (col = 0; col < COL_COUNT * 2; ++col) {
if (master_slave_is_master())
chip_col = (col >= COL_COUNT) ? col - COL_COUNT : -1;
else
chip_col = (col < COL_COUNT) ? col : -1;
if (chip_col >= 0) {
enable_col(chip_col, 1);
STM32_PMSE_MCCR = mccr_list[chip_col];
}
if (master_slave_sync(5) != EC_SUCCESS)
goto fast_scan_err;
start_adc_sample(0, ADC_SMPL_CPU_CYCLE);
while (!(STM32_ADC_SR(0) & (1 << 1)))
;
if (flush_adc(0) >= COL_THRESHOLD)
set_scan_needed(col);
if (master_slave_sync(5) != EC_SUCCESS)
goto fast_scan_err;
if (chip_col >= 0) {
enable_col(chip_col, 0);
STM32_PMSE_MCCR = 0;
}
}
STM32_PMSE_MRCR = 0;
/* Discharge the panel */
discharge();
return EC_SUCCESS;
fast_scan_err:
enable_col(chip_col, 0);
STM32_PMSE_MCCR = 0;
STM32_PMSE_MRCR = 0;
return EC_ERROR_UNKNOWN;
}
#else
#define fast_scan(x) EC_SUCCESS
#endif
void scan_column(uint8_t *data)
{
int i;
STM32_PMSE_MRCR = mrcr_list[0];
start_adc_sample(0, ADC_SMPL_CPU_CYCLE);
STM32_PMSE_MRCR = mrcr_list[1];
start_adc_sample(1, ADC_SMPL_CPU_CYCLE);
for (i = 2; i < ROW_COUNT; ++i) {
data[i - 2] = flush_adc(i & 1);
STM32_PMSE_MRCR = mrcr_list[i];
start_adc_sample(i & 1, ADC_SMPL_CPU_CYCLE);
}
while (!(STM32_ADC_SR(ROW_COUNT & 1) & (1 << 1)))
;
data[ROW_COUNT - 2] = flush_adc(ROW_COUNT & 1);
while (!(STM32_ADC_SR((ROW_COUNT & 1) ^ 1) & (1 << 1)))
;
data[ROW_COUNT - 1] = flush_adc((ROW_COUNT & 1) ^ 1);
}
void touch_scan_slave_start(void)
{
int col = 0, i, v;
struct spi_comm_packet *resp = (struct spi_comm_packet *)buf;
if (fast_scan(scan_needed) != EC_SUCCESS)
goto slave_err;
for (col = 0; col < COL_COUNT * 2; ++col) {
if (col < COL_COUNT) {
enable_col(col, 1);
STM32_PMSE_MCCR = mccr_list[col];
}
if (master_slave_sync(20) != EC_SUCCESS)
goto slave_err;
if (GET_SCAN_NEEDED(col)) {
scan_column(resp->data);
/* Reverse the scanned data */
for (i = 0; ROW_COUNT - 1 - i > i; ++i) {
v = resp->data[i];
resp->data[i] = resp->data[ROW_COUNT - 1 - i];
resp->data[ROW_COUNT - 1 - i] = v;
}
resp->size = ROW_COUNT;
} else {
resp->size = 0;
}
resp->cmd_sts = EC_SUCCESS;
/* Flush the last response */
if (col != 0)
if (spi_slave_send_response_flush() != EC_SUCCESS)
goto slave_err;
/* Start sending the response for the current column */
if (spi_slave_send_response_async(resp) != EC_SUCCESS)
goto slave_err;
/* Disable the current column and discharge */
if (col < COL_COUNT) {
enable_col(col, 0);
STM32_PMSE_MCCR = 0;
}
discharge();
}
spi_slave_send_response_flush();
master_slave_sync(20);
return;
slave_err:
if (col < COL_COUNT)
enable_col(col, 0);
STM32_PMSE_MCCR = 0;
spi_slave_send_response_flush();
}
int touch_scan_full_matrix(void)
{
struct spi_comm_packet cmd;
const struct spi_comm_packet *resp;
int col = 0;
timestamp_t st = get_time();
uint8_t *dptr = NULL, *last_dptr = NULL;
cmd.cmd_sts = TS_CMD_FULL_SCAN;
cmd.size = 0;
if (spi_master_send_command(&cmd))
goto master_err;
encode_reset();
if (fast_scan(scan_needed) != EC_SUCCESS)
goto master_err;
for (col = 0; col < COL_COUNT * 2; ++col) {
if (col >= COL_COUNT) {
enable_col(col - COL_COUNT, 1);
STM32_PMSE_MCCR = mccr_list[col - COL_COUNT];
}
if (master_slave_sync(20) != EC_SUCCESS)
goto master_err;
last_dptr = dptr;
dptr = buf[col & 1];
if (GET_SCAN_NEEDED(col))
scan_column(dptr + ROW_COUNT);
else
memset(dptr + ROW_COUNT, 0, ROW_COUNT);
if (col > 0) {
/* Flush the data from the slave for the last column */
resp = spi_master_wait_response_done();
if (resp == NULL)
goto master_err;
if (resp->size)
memcpy(last_dptr, resp->data, ROW_COUNT);
else
memset(last_dptr, 0, ROW_COUNT);
encode_add_column(last_dptr);
}
/* Start receiving data for the current column */
if (spi_master_wait_response_async() != EC_SUCCESS)
goto master_err;
/* Disable the current column and discharge */
if (col >= COL_COUNT) {
enable_col(col - COL_COUNT, 0);
STM32_PMSE_MCCR = 0;
}
discharge();
}
resp = spi_master_wait_response_done();
if (resp == NULL)
goto master_err;
if (resp->size)
memcpy(last_dptr, resp->data, ROW_COUNT);
else
memset(last_dptr, 0, ROW_COUNT);
encode_add_column(last_dptr);
master_slave_sync(20);
debug_printf("Sampling took %d us\n", get_time().val - st.val);
encode_dump_matrix();
return EC_SUCCESS;
master_err:
spi_master_wait_response_done();
if (col >= COL_COUNT)
enable_col(col - COL_COUNT, 0);
STM32_PMSE_MCCR = 0;
return EC_ERROR_UNKNOWN;
}

77
board/keyborg/touch_scan.h
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@@ -1,77 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Touch scanning module */
#ifndef __BOARD_KEYBORG_TOUCH_SCAN_H
#define __BOARD_KEYBORG_TOUCH_SCAN_H
enum pin_type {
PIN_ROW,
PIN_COL,
PIN_PD,
PIN_Z,
};
/* 8-bit window */
#define ADC_WINDOW_POS 2
/* Threshold for each cell */
#define THRESHOLD 35
/* Threshold for entire column */
#define COL_THRESHOLD 16
/* The span width of active columns */
#define COL_SPAN 5 /* Must not exceed 15 */
/* ADC speed */
#define ADC_SMPR_VAL 0x2 /* 13.5 cycles */
#define ADC_SMPL_CYCLE_2 27
#define ADC_QUNTZ_CYCLE_2 25 /* Quantization always takes 12.5 cycles */
/* CPU clock is 4 times faster than ADC clock */
#define ADC_SMPL_CPU_CYCLE (ADC_SMPL_CYCLE_2 * 2)
struct ts_pin {
uint8_t port_id; /* GPIO_A = 0, GPIO_B = 1, ... */
uint8_t pin;
};
#define TS_GPIO_A 0
#define TS_GPIO_B 1
#define TS_GPIO_C 2
#define TS_GPIO_D 3
#define TS_GPIO_E 4
#define TS_GPIO_F 5
#define TS_GPIO_G 6
#define TS_GPIO_H 7
#define TS_GPIO_I 8
extern const struct ts_pin row_pins[];
extern const struct ts_pin col_pins[];
#define ROW_COUNT 41
#define COL_COUNT 60
/* Initialize touch scan module */
void touch_scan_init(void);
/* Start scanning on the slave. This is called by SPI command handler. */
void touch_scan_slave_start(void);
/**
* Initiate full matrix scan on the master. This also sends SPI command
* to the slave.
*/
int touch_scan_full_matrix(void);
/* Configure touch scan module to interrupt on touch. */
void touch_scan_enable_interrupt(void);
/* Disable touch scan interrupt. */
void touch_scan_disable_interrupt(void);
#endif /* __BOARD_KEYBORG_TOUCH_SCAN_H */

1
board/link/Makefile
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@@ -1 +0,0 @@
../../Makefile

158
board/link/board.c
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@@ -1,158 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* EC for Link board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "backlight.h"
#include "chipset.h"
#include "common.h"
#include "driver/temp_sensor/tmp006.h"
#include "extpower.h"
#include "fan.h"
#include "gpio.h"
#include "i2c.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "peci.h"
#include "power.h"
#include "power_button.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "switch.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "timer.h"
#include "thermal.h"
#include "util.h"
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_PGOOD_5VALW, 1, "PGOOD_5VALW"},
{GPIO_PGOOD_1_5V_DDR, 1, "PGOOD_1_5V_DDR"},
{GPIO_PGOOD_1_5V_PCH, 1, "PGOOD_1_5V_PCH"},
{GPIO_PGOOD_1_8VS, 1, "PGOOD_1_8VS"},
{GPIO_PGOOD_VCCP, 1, "PGOOD_VCCP"},
{GPIO_PGOOD_VCCSA, 1, "PGOOD_VCCSA"},
{GPIO_PGOOD_CPU_CORE, 1, "PGOOD_CPU_CORE"},
{GPIO_PGOOD_VGFX_CORE, 1, "PGOOD_VGFX_CORE"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3#_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4#_DEASSERTED"},
{GPIO_PCH_SLP_S5_L, 1, "SLP_S5#_DEASSERTED"},
{GPIO_PCH_SLP_A_L, 1, "SLP_A#_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
{GPIO_PCH_SLP_ME_CSW_DEV_L, 1, "SLP_ME#_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
const struct adc_t adc_channels[] = {
/* EC internal temperature is calculated by
* 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
* = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
*/
{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
/* Charger current is mapped from 0~4000mA to 0~1.6V.
* And ADC maps 0~3.3V to ADC_READ_MAX.
*/
{"ChargerCurrent", LM4_ADC_SEQ1, 33 * 4000, ADC_READ_MAX * 16, 0,
LM4_AIN(11), 0x06 /* IE0 | END0 */, LM4_GPIO_B, (1<<5)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{1, 0},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_t fans[] = {
{.flags = FAN_USE_RPM_MODE,
.rpm_min = 1500,
.rpm_start = 1500,
.rpm_max = 9300,
.ch = 0,
.pgood_gpio = GPIO_PGOOD_5VALW,
.enable_gpio = -1,
},
};
BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"batt_chg", 0, 100},
{"lightbar", 1, 400},
{"thermal", 5, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
#define TEMP_PCH_REG_ADDR ((0x41 << 1) | I2C_FLAG_BIG_ENDIAN)
#define TEMP_CHARGER_REG_ADDR ((0x43 << 1) | I2C_FLAG_BIG_ENDIAN)
#define TEMP_USB_REG_ADDR ((0x46 << 1) | I2C_FLAG_BIG_ENDIAN)
#define TEMP_HINGE_REG_ADDR ((0x44 << 1) | I2C_FLAG_BIG_ENDIAN)
#define TEMP_PCH_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_PCH_REG_ADDR)
#define TEMP_CHARGER_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_CHARGER_REG_ADDR)
#define TEMP_USB_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_USB_REG_ADDR)
#define TEMP_HINGE_ADDR TMP006_ADDR(I2C_PORT_THERMAL, TEMP_HINGE_REG_ADDR)
/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
const struct temp_sensor_t temp_sensors[] = {
{"I2C-USB C-Die", TEMP_SENSOR_TYPE_IGNORED, tmp006_get_val, 0, 7},
{"I2C-USB C-Object", TEMP_SENSOR_TYPE_IGNORED, tmp006_get_val, 1, 7},
{"I2C-PCH D-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 2, 7},
{"I2C-PCH D-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 3, 7},
{"I2C-Hinge C-Die", TEMP_SENSOR_TYPE_IGNORED, tmp006_get_val, 4, 7},
{"I2C-Hinge C-Object", TEMP_SENSOR_TYPE_IGNORED, tmp006_get_val, 5, 7},
{"I2C-Charger D-Die", TEMP_SENSOR_TYPE_BOARD, tmp006_get_val, 6, 7},
{"I2C-Charger D-Object", TEMP_SENSOR_TYPE_CASE, tmp006_get_val, 7, 7},
{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0, 2},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
/* Only the AP affects the thermal limits and fan speed. */
{{C_TO_K(100), C_TO_K(102), C_TO_K(104)}, C_TO_K(60), C_TO_K(90)},
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
const struct tmp006_t tmp006_sensors[TMP006_COUNT] = {
{"USB C", TEMP_USB_ADDR},
{"PCH D", TEMP_PCH_ADDR},
{"Hinge C", TEMP_HINGE_ADDR},
{"Charger D", TEMP_CHARGER_ADDR},
};
struct keyboard_scan_config keyscan_config = {
.output_settle_us = 40,
.debounce_down_us = 6 * MSEC,
.debounce_up_us = 30 * MSEC,
.scan_period_us = 1500,
.min_post_scan_delay_us = 1000,
.poll_timeout_us = SECOND,
.actual_key_mask = {
0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xc8 /* full set */
},
};

139
board/link/board.h
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@@ -1,139 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Configuration for Link mainboard */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
#define CONFIG_BACKLIGHT_LID
#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
#define CONFIG_BATTERY_LINK
#define CONFIG_BATTERY_SMART
#define CONFIG_BATTERY_OVERRIDE_PARAMS
#define CONFIG_BOARD_VERSION
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V1
#define CONFIG_CHARGER_BQ24725
#define CONFIG_CHIPSET_CAN_THROTTLE
#define CONFIG_CHIPSET_IVYBRIDGE
#define CONFIG_POWER_COMMON
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FANS 1
#define CONFIG_I2C_PASSTHRU_RESTRICTED
#define CONFIG_KEYBOARD_BOARD_CONFIG
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_DRIVER_DS2413
#define CONFIG_ONEWIRE
#define CONFIG_PECI_TJMAX 105
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_PWM
#define CONFIG_PWM_KBLIGHT
#define CONFIG_SWITCH_DEDICATED_RECOVERY
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PGOOD_1_8VS
#define CONFIG_TEMP_SENSOR_TMP006
#define CONFIG_UART_HOST 1
#define CONFIG_USB_PORT_POWER_SMART
#define CONFIG_VBOOT_HASH
#define CONFIG_WIRELESS
#define CONFIG_WP_ACTIVE_HIGH
#ifndef __ASSEMBLER__
enum adc_channel {
/* EC internal die temperature in degrees K. */
ADC_CH_EC_TEMP = 0,
/* Charger current in mA. */
ADC_CH_CHARGER_CURRENT,
ADC_CH_COUNT
};
enum pwm_channel {
PWM_CH_KBLIGHT,
/* Number of PWM channels */
PWM_CH_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* Input sensor resistor, mOhm */
#define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, based on Link HW design */
#define CONFIG_CHARGER_CURRENT_LIMIT 3000 /* PL102 inductor 3.0A(3.8A) */
/* I2C ports */
#define I2C_PORT_BATTERY 0
#define I2C_PORT_CHARGER 0 /* Note: proto0 used port 1 */
#define I2C_PORT_THERMAL 5
#define I2C_PORT_LIGHTBAR 1
#define I2C_PORT_REGULATOR 0
/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
#define KB_SCAN_ROW_IRQ LM4_IRQ_GPION
#define KB_SCAN_ROW_GPIO LM4_GPIO_N
/* Host connects to keyboard controller module via LPC */
#define HOST_KB_BUS_LPC
#include "gpio_signal.h"
/* x86 signal definitions */
enum x86_signal {
X86_PGOOD_5VALW = 0,
X86_PGOOD_1_5V_DDR,
X86_PGOOD_1_5V_PCH,
X86_PGOOD_1_8VS,
X86_PGOOD_VCCP,
X86_PGOOD_VCCSA,
X86_PGOOD_CPU_CORE,
X86_PGOOD_VGFX_CORE,
X86_SLP_S3_DEASSERTED,
X86_SLP_S4_DEASSERTED,
X86_SLP_S5_DEASSERTED,
X86_SLP_A_DEASSERTED,
X86_SLP_SUS_DEASSERTED,
X86_SLP_ME_DEASSERTED,
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
enum temp_sensor_id {
/* TMP006 U20, die/object temperature near Mini-DP / USB connectors */
TEMP_SENSOR_I2C_U20_DIE = 0,
TEMP_SENSOR_I2C_U20_OBJECT,
/* TMP006 U11, die/object temperature near PCH */
TEMP_SENSOR_I2C_U11_DIE,
TEMP_SENSOR_I2C_U11_OBJECT,
/* TMP006 U27, die/object temperature near hinge */
TEMP_SENSOR_I2C_U27_DIE,
TEMP_SENSOR_I2C_U27_OBJECT,
/* TMP006 U14, die/object temperature near battery charger */
TEMP_SENSOR_I2C_U14_DIE,
TEMP_SENSOR_I2C_U14_OBJECT,
/* EC internal temperature sensor */
TEMP_SENSOR_EC_INTERNAL,
/* CPU die temperature via PECI */
TEMP_SENSOR_CPU_PECI,
TEMP_SENSOR_COUNT
};
/* The number of TMP006 sensor chips on the board. */
#define TMP006_COUNT 4
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_RADIO_ENABLE_WLAN
#define WIRELESS_GPIO_BLUETOOTH GPIO_RADIO_ENABLE_BT
#define WIRELESS_GPIO_WLAN_POWER GPIO_ENABLE_WLAN
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

12
board/link/build.mk
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@@ -1,12 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is TI Stellaris LM4
CHIP:=lm4
board-y=board.o

28
board/link/ec.tasklist
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@@ -1,28 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' is the name of the task
* 'r' is the main routine of the task
* 'd' is an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(LIGHTBAR, lightbar_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

96
board/link/gpio.inc
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@@ -1,96 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(POWER_BUTTON_L, PIN(K, 7), GPIO_INT_BOTH, power_button_interrupt) /* Power button */
GPIO_INT(LID_OPEN, PIN(K, 5), GPIO_INT_BOTH, lid_interrupt) /* Lid switch */
GPIO_INT(AC_PRESENT, PIN(H, 3), GPIO_INT_BOTH, extpower_interrupt) /* AC power present */
GPIO_INT(PCH_BKLTEN, PIN(J, 3), GPIO_INT_BOTH, backlight_interrupt) /* Backlight enable signal from PCH */
GPIO_INT(PCH_SLP_A_L, PIN(G, 5), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_A# signal from PCH */
GPIO_INT(PCH_SLP_ME_CSW_DEV_L, PIN(G, 4), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_ME_CSW_DEV# signal from PCH */
GPIO_INT(PCH_SLP_S3_L, PIN(J, 0), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S3# signal from PCH */
GPIO_INT(PCH_SLP_S4_L, PIN(J, 1), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S4# signal from PCH */
GPIO_INT(PCH_SLP_S5_L, PIN(J, 2), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S5# signal from PCH */
GPIO_INT(PCH_SLP_SUS_L, PIN(G, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_SUS# signal from PCH */
GPIO_INT(PCH_SUSWARN_L, PIN(G, 2), GPIO_INT_BOTH, power_interrupt) /* SUSWARN# signal from PCH */
GPIO_INT(PGOOD_1_5V_DDR, PIN(K, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +1.5V_DDR */
GPIO_INT(PGOOD_1_5V_PCH, PIN(K, 1), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +1.5V_PCH */
GPIO_INT(PGOOD_1_8VS, PIN(K, 3), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +1.8VS */
GPIO_INT(PGOOD_5VALW, PIN(H, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +5VALW */
GPIO_INT(PGOOD_CPU_CORE, PIN(M, 3), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +CPU_CORE */
GPIO_INT(PGOOD_VCCP, PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +VCCP */
GPIO_INT(PGOOD_VCCSA, PIN(H, 1), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +VCCSA */
GPIO_INT(PGOOD_VGFX_CORE, PIN(D, 2), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on +VGFX_CORE */
GPIO_INT(RECOVERY_L, PIN(H, 7), GPIO_INT_BOTH, switch_interrupt) /* Recovery signal from servo */
GPIO_INT(WP, PIN(J, 4), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */
/* Other inputs */
GPIO(THERMAL_DATA_READY_L, PIN(B, 4), GPIO_INPUT) /* Data ready from I2C thermal sensor */
GPIO(BOARD_VERSION1, PIN(H, 6), GPIO_INPUT) /* Board version stuffing resistor 1 */
GPIO(BOARD_VERSION2, PIN(L, 6), GPIO_INPUT) /* Board version stuffing resistor 2 */
GPIO(BOARD_VERSION3, PIN(L, 7), GPIO_INPUT) /* Board version stuffing resistor 3 */
GPIO(ONEWIRE, PIN(H, 2), GPIO_INPUT) /* One-wire bus to adapter LED */
GPIO(USB1_STATUS_L, PIN(E, 7), GPIO_INPUT) /* USB charger port 1 status output */
GPIO(USB2_STATUS_L, PIN(E, 1), GPIO_INPUT) /* USB charger port 2 status output */
/* Outputs; all unasserted by default except for reset signals */
GPIO(CPU_PROCHOT, PIN(F, 2), GPIO_OUT_LOW) /* Force CPU to think it's overheated */
GPIO(ENABLE_1_5V_DDR, PIN(H, 5), GPIO_OUT_LOW) /* Enable +1.5V_DDR supply */
GPIO(ENABLE_5VALW, PIN(K, 4), GPIO_OUT_HIGH) /* Enable +5V always on rail */
GPIO(ENABLE_BACKLIGHT, PIN(H, 4), GPIO_OUT_LOW) /* Enable backlight power */
GPIO(ENABLE_TOUCHPAD, PIN(C, 6), GPIO_OUT_LOW) /* Enable touchpad power */
GPIO(ENABLE_VCORE, PIN(F, 7), GPIO_OUT_LOW) /* Enable +CPU_CORE and +VGFX_CORE */
GPIO(ENABLE_VS, PIN(G, 6), GPIO_OUT_LOW) /* Enable VS power supplies */
GPIO(ENABLE_WLAN, PIN(Q, 5), GPIO_OUT_LOW) /* Enable WLAN module power (+3VS_WLAN) */
GPIO(ENTERING_RW, PIN(J, 5), GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(LIGHTBAR_RESET_L, PIN(B, 1), GPIO_OUT_LOW) /* Reset lightbar controllers */
GPIO(PCH_A20GATE, PIN(Q, 6), GPIO_OUT_LOW) /* A20GATE signal to PCH */
GPIO(PCH_DPWROK, PIN(G, 0), GPIO_OUT_LOW) /* DPWROK signal to PCH */
/*
* HDA_SDO is technically an output, but we need to leave it as an
* input until we drive it high. So can't use open-drain (HI_Z).
*/
GPIO(PCH_HDA_SDO, PIN(G, 1), GPIO_INPUT) /* HDA_SDO signal to PCH; when high, ME ignores security descriptor */
GPIO(PCH_WAKE_L, PIN(F, 0), GPIO_OUT_HIGH) /* Wake signal output to PCH */
GPIO(PCH_NMI_L, PIN(M, 2), GPIO_OUT_HIGH) /* Non-maskable interrupt pin to PCH */
GPIO(PCH_PWRBTN_L, PIN(G, 7), GPIO_OUT_HIGH) /* Power button output to PCH */
GPIO(PCH_PWROK, PIN(F, 5), GPIO_OUT_LOW) /* PWROK / APWROK signals to PCH */
GPIO(PCH_RCIN_L, PIN(Q, 7), GPIO_ODR_HIGH) /* RCIN# signal to PCH */
GPIO(PCH_RSMRST_L, PIN(F, 1), GPIO_OUT_LOW) /* Reset PCH resume power plane logic */
GPIO(PCH_RTCRST_L, PIN(F, 6), GPIO_ODR_HIGH) /* Reset PCH RTC well */
GPIO(PCH_SMI_L, PIN(F, 4), GPIO_OUT_HIGH) /* System management interrupt to PCH */
GPIO(PCH_SRTCRST_L, PIN(C, 7), GPIO_ODR_HIGH) /* Reset PCH ME RTC well */
GPIO(PCH_SUSACK_L, PIN(F, 3), GPIO_OUT_HIGH) /* Acknowledge PCH SUSWARN# signal */
GPIO(RADIO_ENABLE_WLAN, PIN(D, 0), GPIO_OUT_LOW) /* Enable WLAN radio */
GPIO(RADIO_ENABLE_BT, PIN(D, 1), GPIO_OUT_LOW) /* Enable bluetooth radio */
GPIO(SPI_CS_L, PIN(A, 3), GPIO_ODR_HIGH) /* SPI chip select */
GPIO(TOUCHSCREEN_RESET_L, PIN(B, 0), GPIO_OUT_LOW) /* Reset touch screen */
GPIO(USB1_CTL1, PIN(E, 2), GPIO_OUT_LOW) /* USB charger port 1 CTL1 output */
GPIO(USB1_CTL2, PIN(E, 3), GPIO_OUT_LOW) /* USB charger port 1 CTL2 output */
GPIO(USB1_CTL3, PIN(E, 4), GPIO_OUT_LOW) /* USB charger port 1 CTL3 output */
GPIO(USB1_ENABLE, PIN(E, 5), GPIO_OUT_LOW) /* USB charger port 1 enable */
GPIO(USB1_ILIM_SEL, PIN(E, 6), GPIO_OUT_LOW) /* USB charger port 1 ILIM_SEL output */
GPIO(USB2_CTL1, PIN(D, 4), GPIO_OUT_LOW) /* USB charger port 2 CTL1 output */
GPIO(USB2_CTL2, PIN(D, 5), GPIO_OUT_LOW) /* USB charger port 2 CTL2 output */
GPIO(USB2_CTL3, PIN(D, 6), GPIO_OUT_LOW) /* USB charger port 2 CTL3 output */
GPIO(USB2_ENABLE, PIN(D, 7), GPIO_OUT_LOW) /* USB charger port 2 enable */
GPIO(USB2_ILIM_SEL, PIN(E, 0), GPIO_OUT_LOW) /* USB charger port 2 ILIM_SEL output */
ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART, 0) /* UART0 */
ALTERNATE(PIN_MASK(A, 0x40), 3, MODULE_I2C, 0) /* I2C1 SCL */
ALTERNATE(PIN_MASK(A, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C1 SDA */
ALTERNATE(PIN_MASK(B, 0x04), 3, MODULE_I2C, 0) /* I2C0 SCL */
ALTERNATE(PIN_MASK(B, 0x08), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C0 SDA */
ALTERNATE(PIN_MASK(B, 0x40), 3, MODULE_I2C, 0) /* I2C5 SCL */
ALTERNATE(PIN_MASK(B, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C5 SDA */
ALTERNATE(PIN_MASK(C, 0x30), 2, MODULE_UART, 0) /* UART1 */
ALTERNATE(PIN_MASK(J, 0x40), 1, MODULE_PECI, 0) /* PECI Tx */
ALTERNATE(PIN_MASK(J, 0x80), 0, MODULE_PECI, GPIO_ANALOG) /* PECI Rx */
ALTERNATE(PIN_MASK(K, 0x40), 1, MODULE_PWM_KBLIGHT, 0) /* FAN0PWM1 */
ALTERNATE(PIN_MASK(L, 0x3f), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(M, 0x33), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(M, 0xc0), 1, MODULE_PWM_FAN, 0) /* FAN0PWM0 */

3
board/link/userspace/README
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@@ -1,3 +0,0 @@
Sometimes we need to perform some run-time tweaks of the EC from the AP's
userspace. This directory holds those tweaks. They're picked up by the
ec-utils ebuild.

13
board/link/userspace/etc/init/ec.conf
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@@ -1,13 +0,0 @@
# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
description "Overrides lightbar params to tweak appearance"
author "chromium-os-dev@chromium.org"
start on startup
script
PARAMS=/usr/share/ec/lightbar_params.txt
[ -f "$PARAMS" ] && ectool lightbar params "$PARAMS" >/dev/null 2>&1
end script

31
board/link/userspace/usr/share/ec/lightbar_params.txt
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@@ -1,31 +0,0 @@
2500 # .google_ramp_up
10000 # .google_ramp_down
2000 # .s3s0_ramp_up
45000 # .s0_tick_delay (battery)
30000 # .s0_tick_delay (AC)
5000 # .s0a_tick_delay (battery)
3000 # .s0a_tick_delay (AC)
2000 # .s0s3_ramp_down
5000000 # .s3_sleep_for
2500 # .s3_ramp_up
10000 # .s3_ramp_down
1 # .new_s0
0x60 0x60 # .osc_min (battery, AC)
0xd0 0xd0 # .osc_max (battery, AC)
24 24 # .w_ofs (battery, AC)
0xcc 0xff # .bright_bl_off_fixed (battery, AC)
0xcc 0xff # .bright_bl_on_min (battery, AC)
0xcc 0xff # .bright_bl_on_max (battery, AC)
14 40 99 # .battery_threshold
5 4 4 4 # .s0_idx[] (battery)
4 4 4 4 # .s0_idx[] (AC)
5 255 255 255 # .s3_idx[] (battery)
255 255 255 255 # .s3_idx[] (AC)
0x33 0x69 0xe8 # color[0]
0xd5 0x0f 0x25 # color[1]
0xee 0xb2 0x11 # color[2]
0x00 0x99 0x25 # color[3]
0x00 0x00 0xff # color[4]
0xff 0x00 0x00 # color[5]
0xff 0xff 0x00 # color[6]
0x00 0xff 0x00 # color[7]

1
board/mccroskey/Makefile
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@@ -1 +0,0 @@
../../Makefile

87
board/mccroskey/board.c
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@@ -1,87 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* McCroskey board-specific configuration */
#include "chipset.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "i2c.h"
#include "keyboard_raw.h"
#include "registers.h"
#include "spi.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#define GPIO_KB_OUTPUT (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_OUT_LOW)
#define HARD_RESET_TIMEOUT_MS 5
#include "gpio_list.h"
void board_config_pre_init(void)
{
uint32_t val;
/* Enable all GPIOs clocks.
*
* TODO(crosbug.com/p/23494): more fine-grained enabling for power
* saving.
*/
STM32_RCC_APB2ENR |= 0x1fd;
#ifdef CONFIG_SPI
/*
* SPI1 on pins PA4-7 (alt. function push-pull, 10MHz).
*
* TODO(crosbug.com/p/23494): Connected device SPI freq is fxo/2 in
* master mode, fxo/4 in slave mode. fxo ranges from 12-40MHz.
*/
val = STM32_GPIO_CRL(GPIO_A) & ~0xffff0000;
val |= 0x99990000;
STM32_GPIO_CRL(GPIO_A) = val;
#endif
/* remap OSC_IN/OSC_OUT to PD0/PD1 */
STM32_GPIO_AFIO_MAPR |= 1 << 15;
/* use PB3 as a GPIO, so disable JTAG and keep only SWD */
STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24))
| (2 << 24);
/* remap TIM2_CH2 to PB3 */
STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x3 << 8))
| (1 << 8);
/*
* Set alternate function for USART1. For alt. function input
* the port is configured in either floating or pull-up/down
* input mode (ref. section 7.1.4 in datasheet RM0041):
* PA9: Tx, alt. function output
* PA10: Rx, input with pull-down
*
* note: see crosbug.com/p/12223 for more info
*/
val = STM32_GPIO_CRH(GPIO_A) & ~0x00000ff0;
val |= 0x00000890;
STM32_GPIO_CRH(GPIO_A) = val;
}
/* GPIO configuration to be done after I2C module init */
void board_i2c_post_init(int port)
{
uint32_t val;
/* enable alt. function (open-drain) */
if (port == STM32_I2C1_PORT) {
/* I2C1 is on PB6-7 */
val = STM32_GPIO_CRL(GPIO_B) & ~0xff000000;
val |= 0xdd000000;
STM32_GPIO_CRL(GPIO_B) = val;
}
}

52
board/mccroskey/board.h
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@@ -1,52 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* McCroskey board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* Debug features */
/* TODO(crosbug.com/p/23494): turn off extra I2C debugging when it works */
#define CONFIG_I2C_DEBUG
#undef CONFIG_TASK_PROFILING
/* Features not present on this reference board */
#undef CONFIG_LID_SWITCH
/* Optional features */
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_KEYBOARD_PROTOCOL_MKBP
/*
* TODO(crosbug.com/p/23494): Stop mode causes the UART to drop characters and
* likely other bad side-effects. Disable for now.
*/
#undef CONFIG_LOW_POWER_IDLE
#ifndef __ASSEMBLER__
/* Keyboard output ports */
#define KB_OUT_PORT_LIST GPIO_C
/* EC is I2C master */
#define I2C_PORT_MASTER 0
#define I2C_PORT_SLAVE 0 /* needed for DMAC macros (ugh) */
#define GPIO_I2C2_SCL 0 /* unused, but must be defined anyway */
#define GPIO_I2C2_SDA 0 /* unused, but must be defined anyway */
/* Timer selection */
#define TIM_CLOCK_MSB 3
#define TIM_CLOCK_LSB 4
#define TIM_WATCHDOG 1
#include "gpio_signal.h"
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

13
board/mccroskey/build.mk
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@@ -1,13 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F102R8
CHIP:=stm32
CHIP_FAMILY:=stm32f
CHIP_VARIANT:=stm32f10x
board-y=board.o

23
board/mccroskey/ec.tasklist
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@@ -1,23 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, 360)

73
board/mccroskey/gpio.inc
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@@ -1,73 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(KB_IN00, PIN(B, 8), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN01, PIN(B, 9), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN02, PIN(B, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN03, PIN(B, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN04, PIN(B, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN05, PIN(B, 13), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN06, PIN(B, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN07, PIN(B, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
/* TODO(crosbug.com/p/23494): interrupt handler for power button */
GPIO(KBD_PWR_BUTTON, PIN(B, 2), GPIO_INPUT)
GPIO(OMZO_RDY_L, PIN(A, 0), GPIO_INPUT) /* PA0_WKUP */
GPIO(OZMO_RST_L, PIN(A, 2), GPIO_ODR_HIGH)
GPIO(VBUS_UP_DET, PIN(A, 3), GPIO_INPUT)
GPIO(OZMO_REQ_L, PIN(A, 8), GPIO_INPUT)
GPIO(CHARGE_ZERO, PIN(B, 0), GPIO_INPUT)
GPIO(CHARGE_SHUNT, PIN(B, 1), GPIO_INPUT)
GPIO(PMIC_INT_L, PIN(B, 5), GPIO_INPUT)
/*
* I2C pins should be configured as inputs until I2C module is
* initialized. This will avoid driving the lines unintentionally.
*/
GPIO(I2C1_SCL, PIN(B, 6), GPIO_INPUT)
GPIO(I2C1_SDA, PIN(B, 7), GPIO_INPUT)
GPIO(KB_OUT00, PIN(C, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT01, PIN(C, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT02, PIN(C, 2), GPIO_KB_OUTPUT)
GPIO(KB_OUT03, PIN(C, 3), GPIO_KB_OUTPUT)
GPIO(KB_OUT04, PIN(C, 4), GPIO_KB_OUTPUT)
GPIO(KB_OUT05, PIN(C, 5), GPIO_KB_OUTPUT)
GPIO(KB_OUT06, PIN(C, 6), GPIO_KB_OUTPUT)
GPIO(KB_OUT07, PIN(C, 7), GPIO_KB_OUTPUT)
GPIO(KB_OUT08, PIN(C, 8), GPIO_KB_OUTPUT)
GPIO(KB_OUT09, PIN(C, 9), GPIO_KB_OUTPUT)
GPIO(KB_OUT10, PIN(C, 10), GPIO_KB_OUTPUT)
GPIO(KB_OUT11, PIN(C, 11), GPIO_KB_OUTPUT)
GPIO(KB_OUT12, PIN(C, 12), GPIO_KB_OUTPUT)
GPIO(USB_VBUS_CTRL, PIN(C, 13), GPIO_OUT_LOW)
GPIO(HUB_RESET, PIN(C, 14), GPIO_ODR_HIGH)
GPIO(WP_L, PIN(D, 2), GPIO_INPUT)
/*
* TODO(crosbug.com/p/23494): This will be an alternate function GPIO,
* so remove it from here.
*/
GPIO(BL_PWM, PIN(A, 1), GPIO_OUTPUT)
/* Unimplemented signals which we need to emulate for now */
UNIMPLEMENTED(EC_INT)
UNIMPLEMENTED(ENTERING_RW)
#if 0
/* Other GPIOs (probably need to be set up below as alt. function) */
GPIO(STM_USBDM, PIN(A, 11), GPIO_DEFAULT)
GPIO(STM_USBDP, PIN(A, 12), GPIO_DEFAULT)
GPIO(JTMS_SWDIO, PIN(A, 13), GPIO_DEFAULT)
GPIO(JTCK_SWCLK, PIN(A, 14), GPIO_DEFAULT)
GPIO(JTDI, PIN(A, 15), GPIO_DEFAULT)
GPIO(JTDO, PIN(B, 3), GPIO_DEFAULT)
GPIO(JNTRST, PIN(B, 4), GPIO_DEFAULT)
GPIO(OSC32_OUT, PIN(C, 15), GPIO_DEFAULT)
#endif

1
board/mighty/Makefile
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../../Makefile

54
board/mighty/battery.c
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/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "console.h"
#include "gpio.h"
#include "host_command.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHUTDOWN_DATA 0x0010
static const struct battery_info info = {
.voltage_max = 8400, /* mV */
.voltage_normal = 7400,
.voltage_min = 6000,
.precharge_current = 256, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 45,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
static int cutoff(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
}
int board_cut_off_battery(void)
{
return cutoff();
}

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board/mighty/board.c
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Veyron board-specific configuration */
#include "battery.h"
#include "chipset.h"
#include "common.h"
#include "extpower.h"
#include "gpio.h"
#include "i2c.h"
#include "keyboard_raw.h"
#include "lid_switch.h"
#include "power.h"
#include "power_button.h"
#include "power.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "spi.h"
#include "task.h"
#include "util.h"
#include "timer.h"
#include "charger.h"
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_SOC_POWER_GOOD, 1, "POWER_GOOD"},
{GPIO_SUSPEND_L, 1, "SUSPEND#_ASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{STM32_TIM(2), STM32_TIM_CH(3),
PWM_CONFIG_ACTIVE_LOW},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
/**
* Discharge battery when on AC power for factory test.
*/
int board_discharge_on_ac(int enable)
{
return charger_discharge_on_ac(enable);
}
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
/* Remap USART DMA to match the USART driver */
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1
* Chan 3 : SPI1_TX
* Chan 4 : USART1_TX
* Chan 5 : USART1_RX
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
}

88
board/mighty/board.h
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Veyron board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_CHARGER
#define CONFIG_CHARGER_BQ24715
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_V2
#define CONFIG_CHIPSET_ROCKCHIP
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HOST_COMMAND_STATUS
#define CONFIG_I2C
#define CONFIG_KEYBOARD_COL2_INVERTED
#define CONFIG_KEYBOARD_PROTOCOL_MKBP
#define CONFIG_LED_COMMON
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LOW_POWER_S0
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1
#define CONFIG_POWER_COMMON
#define CONFIG_PWM
#define CONFIG_SPI
#define CONFIG_STM_HWTIMER32
#define CONFIG_UART_RX_DMA
#define CONFIG_VBOOT_HASH
#undef CONFIG_WATCHDOG_HELP
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1 | STM32_PWR_CSR_EWUP6)
#ifndef __ASSEMBLER__
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* Keyboard output port list */
#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C
/* Single I2C port, where the EC is the master. */
#define I2C_PORT_MASTER 0
#define I2C_PORT_BATTERY I2C_PORT_MASTER
#define I2C_PORT_CHARGER I2C_PORT_MASTER
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_WATCHDOG 4
#include "gpio_signal.h"
enum power_signal {
RK_POWER_GOOD = 0,
RK_SUSPEND_ASSERTED,
/* Number of power signals */
POWER_SIGNAL_COUNT
};
enum pwm_channel {
PWM_CH_POWER_LED = 0,
/* Number of PWM channels */
PWM_CH_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* Input sensor resistor, mOhm */
/* Input current limit for 45W AC adapter:
* 45W/19V*85%=2013mA, choose the closest charger setting = 2048mA
*/
#define CONFIG_CHARGER_INPUT_CURRENT 2048 /* mA, based on Link HW design */
#define CONFIG_CHARGER_CURRENT_LIMIT 3000 /* PL102 inductor 3.0A(3.8A) */
/* Discharge battery when on AC power for factory test. */
int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

13
board/mighty/build.mk
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# -*- makefile -*-
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F071RB
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f07x
board-y=board.o battery.o led.o

23
board/mighty/ec.tasklist
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK(n, r, d, s) where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

59
board/mighty/gpio.inc
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/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(POWER_BUTTON_L, PIN(B, 5), GPIO_INT_BOTH, power_button_interrupt) /* wk6 */ /* active high, the name is for compatibility with existing code */
GPIO_INT(SOC_POWER_GOOD, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(LID_OPEN, PIN(C, 13), GPIO_INT_BOTH, lid_interrupt)
GPIO_INT(SUSPEND_L, PIN(C, 7), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INT_BOTH, spi_event)
GPIO_INT(AC_PRESENT, PIN(A, 8), GPIO_INT_BOTH | GPIO_PULL_UP, extpower_interrupt)
/* Keyboard inputs */
GPIO_INT(KB_IN00, PIN(C, 8), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN01, PIN(C, 9), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN07, PIN(D, 2), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
/* Other inputs */
GPIO(EC_WAKE, PIN(A, 0), GPIO_INPUT | GPIO_PULL_DOWN) /* wk1 */
GPIO(WP_L, PIN(B, 4), GPIO_INPUT)
/* Outputs */
GPIO(BAT_LED0, PIN(B, 11), GPIO_OUT_LOW)
GPIO(BAT_LED1, PIN(A, 11), GPIO_OUT_LOW)
GPIO(EC_BL_OVERRIDE, PIN(F, 1), GPIO_OUT_LOW)
GPIO(EC_INT, PIN(B, 9), GPIO_OUT_LOW)
GPIO(ENTERING_RW, PIN(F, 0), GPIO_OUT_LOW)
GPIO(I2C1_SCL, PIN(B, 6), GPIO_ODR_HIGH)
GPIO(I2C1_SDA, PIN(B, 7), GPIO_ODR_HIGH)
GPIO(KB_OUT00, PIN(B, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT01, PIN(B, 8), GPIO_KB_OUTPUT)
GPIO(KB_OUT02, PIN(B, 12), GPIO_OUT_LOW) /* Inverted from silegro */
GPIO(KB_OUT03, PIN(B, 13), GPIO_KB_OUTPUT)
GPIO(KB_OUT04, PIN(B, 14), GPIO_KB_OUTPUT)
GPIO(KB_OUT05, PIN(B, 15), GPIO_KB_OUTPUT)
GPIO(KB_OUT06, PIN(C, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT07, PIN(C, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT08, PIN(C, 2), GPIO_KB_OUTPUT)
GPIO(KB_OUT09, PIN(B, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT10, PIN(C, 5), GPIO_KB_OUTPUT)
GPIO(KB_OUT11, PIN(C, 4), GPIO_KB_OUTPUT)
GPIO(KB_OUT12, PIN(A, 13), GPIO_KB_OUTPUT)
GPIO(POWER_LED, PIN(A, 2), GPIO_OUT_LOW)
GPIO(PMIC_PWRON, PIN(A, 12), GPIO_OUT_LOW)
GPIO(PMIC_RESET, PIN(B, 3), GPIO_OUT_LOW)
GPIO(PMIC_SOURCE_PWREN, PIN(B, 10), GPIO_OUT_LOW)
GPIO(PMIC_WARM_RESET_L, PIN(C, 3), GPIO_ODR_HIGH)
ALTERNATE(PIN_MASK(A, 0x00f0), 0, MODULE_SPI, 0)
ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_UART, 0)
ALTERNATE(PIN_MASK(B, 0x00c0), 1, MODULE_I2C, 0)

152
board/mighty/led.c
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery LED and Power LED control for mighty
*/
#include "gpio.h"
#include "hooks.h"
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "led_common.h"
#include "util.h"
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_BATTERY_LED,
EC_LED_ID_POWER_LED,
};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
enum led_color {
LED_GREEN = 0,
LED_ORANGE,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
static int bat_led_set(enum led_color color, int on)
{
switch (color) {
case LED_GREEN:
gpio_set_level(GPIO_BAT_LED1, on ? 0 : 1);
break;
case LED_ORANGE:
gpio_set_level(GPIO_BAT_LED0, on ? 0 : 1);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
static int pwr_led_set(int on)
{
gpio_set_level(GPIO_POWER_LED, on ? 0 : 1);
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
/* Ignoring led_id as both leds support the same colors */
brightness_range[EC_LED_COLOR_GREEN] = 1;
brightness_range[EC_LED_COLOR_YELLOW] = 1;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
if (brightness[EC_LED_COLOR_GREEN] != 0) {
bat_led_set(LED_GREEN, 1);
bat_led_set(LED_ORANGE, 0);
} else if (brightness[EC_LED_COLOR_YELLOW] != 0) {
bat_led_set(LED_GREEN, 1);
bat_led_set(LED_ORANGE, 1);
} else {
bat_led_set(LED_GREEN, 0);
bat_led_set(LED_ORANGE, 0);
}
break;
case EC_LED_ID_POWER_LED:
pwr_led_set(brightness[EC_LED_COLOR_BLUE]);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
static void mighty_led_set_power(void)
{
static int power_second;
power_second++;
/* PWR LED behavior:
* Power on: Green
* Suspend: Green in breeze mode ( 1 sec on/ 3 sec off)
* Power off: OFF
*/
if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
pwr_led_set(0);
else if (chipset_in_state(CHIPSET_STATE_ON))
pwr_led_set(1);
else if (chipset_in_state(CHIPSET_STATE_SUSPEND))
pwr_led_set((power_second & 3) ? 0 : 1);
}
static void mighty_led_set_battery(void)
{
static int battery_second;
battery_second++;
/* BAT LED behavior:
* Fully charged / idle: Off
* Under charging: Orange
* Battery low (10%): Orange in breeze mode (1 sec on, 3 sec off)
* Battery critical low (less than 3%) or abnormal battery
* situation: Orange in blinking mode (1 sec on, 1 sec off)
* Using battery or not connected to AC power: OFF
*/
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
bat_led_set(LED_ORANGE, 1);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
bat_led_set(LED_ORANGE, 1);
break;
case PWR_STATE_DISCHARGE:
if (charge_get_percent() < 3)
bat_led_set(LED_ORANGE, (battery_second & 1) ? 0 : 1);
else if (charge_get_percent() < 10)
bat_led_set(LED_ORANGE, (battery_second & 3) ? 0 : 1);
else
bat_led_set(LED_ORANGE, 0);
break;
case PWR_STATE_ERROR:
bat_led_set(LED_ORANGE, (battery_second & 1) ? 0 : 1);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE. */
bat_led_set(LED_ORANGE, 0);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/** * Called by hook task every 1 sec */
static void led_second(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
mighty_led_set_power();
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
mighty_led_set_battery();
}
DECLARE_HOOK(HOOK_SECOND, led_second, HOOK_PRIO_DEFAULT);

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board/nyan/Makefile
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../../Makefile

275
board/nyan/battery.c
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@@ -1,275 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "gpio.h"
#include "host_command.h"
#include "util.h"
#include "console.h"
/* Console output macros */
#define CPRINTS(format, args...) cprints(CC_CHARGER, format, ## args)
/* These 2 defines are for cut_off command for 3S battery */
#define SB_SHIP_MODE_ADDR 0x3a
#define SB_SHIP_MODE_DATA 0xc574
static struct battery_info *battery_info;
static int support_cut_off;
struct battery_device {
char manuf[9];
char device[9];
int design_mv;
struct battery_info *battery_info;
int support_cut_off;
};
/*
* Used for the case that battery cannot be detected, such as the pre-charge
* case. In this case, we need to provide the battery with the enough voltage
* (usually the highest voltage among batteries, but the smallest precharge
* current). This should be as conservative as possible.
*/
static struct battery_info info_precharge = {
/*
* Design voltage
* max = 8.4V
* normal = 7.4V
* min = 6.0V
*/
.voltage_max = 12600, /* the max voltage among batteries */
.voltage_normal = 11100,
.voltage_min = 9000,
/* Pre-charge current: I <= 0.01C */
.precharge_current = 64, /* mA, the min current among batteries */
/*
* Operational temperature range
* 0 <= T_charge <= 50 deg C
* -20 <= T_discharge <= 60 deg C
*/
.start_charging_min_c = 0,
.start_charging_max_c = 50,
.charging_min_c = 0,
.charging_max_c = 50,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
static struct battery_info info_2s = {
/*
* Design voltage
* max = 8.4V
* normal = 7.4V
* min = 6.0V
*/
.voltage_max = 8400,
.voltage_normal = 7400,
.voltage_min = 6000,
/* Pre-charge current: I <= 0.01C */
.precharge_current = 64, /* mA */
/*
* Operational temperature range
* 0 <= T_charge <= 50 deg C
* -20 <= T_discharge <= 60 deg C
*/
.start_charging_min_c = 0,
.start_charging_max_c = 50,
.charging_min_c = 0,
.charging_max_c = 50,
.discharging_min_c = -20,
.discharging_max_c = 60,
};
static struct battery_info info_3s = {
.voltage_max = 12600,
.voltage_normal = 11100, /* Average of max & min */
.voltage_min = 9000,
/* Pre-charge values. */
.precharge_current = 392, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 60,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = 0,
.discharging_max_c = 50,
};
static const struct battery_device support_batteries[] = {
{
.manuf = "NVT",
.device = "ARROW",
.design_mv = 7400,
.battery_info = &info_2s,
.support_cut_off = 0,
},
{
.manuf = "SANYO",
.device = "AP13J3K",
.design_mv = 11250,
.battery_info = &info_3s,
.support_cut_off = 1,
},
{
.manuf = "SONYCorp",
.device = "AP13J4K",
.design_mv = 11400,
.battery_info = &info_3s,
.support_cut_off = 1,
}
};
#ifdef CONFIG_BATTERY_OVERRIDE_PARAMS
/*
* The following parameters are for 2S battery.
* There is no corresponding params for 3S battery.
*/
enum {
TEMP_RANGE_10,
TEMP_RANGE_23,
TEMP_RANGE_35,
TEMP_RANGE_45,
TEMP_RANGE_50,
TEMP_RANGE_MAX
};
enum {
VOLT_RANGE_7200,
VOLT_RANGE_8000,
VOLT_RANGE_8400,
VOLT_RANGE_MAX
};
/*
* Vendor provided charging method
* temp : < 7.2V, 7.2V ~ 8.0V, 8.0V ~ 8.4V
* - 0 ~ 10 : 0.8A 1.6A 0.8A
* - 10 ~ 23 : 1.6A 4.0A 1.6A
* - 23 ~ 35 : 4.0A 4.0A 4.0A
* - 35 ~ 45 : 1.6A 4.0A 1.6A
* - 45 ~ 50 : 0.8A 1.6A 0.8A
*/
static const int const current_limit[TEMP_RANGE_MAX][VOLT_RANGE_MAX] = {
{ 800, 1600, 800},
{1600, 4000, 1600},
{4000, 4000, 4000},
{1600, 4000, 1600},
{ 800, 1600, 800},
};
static inline void limit_value(int *val, int limit)
{
if (*val > limit)
*val = limit;
}
void battery_override_params(struct batt_params *batt)
{
int *desired_current = &batt->desired_current;
int temp_range, volt_range;
int bat_temp_c = DECI_KELVIN_TO_CELSIUS(batt->temperature);
if (battery_info == NULL)
return;
/* Return if the battery is not a 2S battery */
if (battery_info->voltage_max != info_2s.voltage_max)
return;
/* Limit charging voltage */
if (batt->desired_voltage > battery_info->voltage_max)
batt->desired_voltage = battery_info->voltage_max;
/* Don't charge if outside of allowable temperature range */
if (bat_temp_c >= battery_info->charging_max_c ||
bat_temp_c < battery_info->charging_min_c) {
batt->desired_voltage = 0;
batt->desired_current = 0;
batt->flags &= ~BATT_FLAG_WANT_CHARGE;
return;
}
if (bat_temp_c <= 10)
temp_range = TEMP_RANGE_10;
else if (bat_temp_c <= 23)
temp_range = TEMP_RANGE_23;
else if (bat_temp_c <= 35)
temp_range = TEMP_RANGE_35;
else if (bat_temp_c <= 45)
temp_range = TEMP_RANGE_45;
else
temp_range = TEMP_RANGE_50;
if (batt->voltage < 7200)
volt_range = VOLT_RANGE_7200;
else if (batt->voltage < 8000)
volt_range = VOLT_RANGE_8000;
else
volt_range = VOLT_RANGE_8400;
limit_value(desired_current, current_limit[temp_range][volt_range]);
/* If battery wants current, give it at least the precharge current */
if (*desired_current > 0 &&
*desired_current < battery_info->precharge_current)
*desired_current = battery_info->precharge_current;
}
#endif /* CONFIG_BATTERY_OVERRIDE_PARAMS */
const struct battery_info *battery_get_info(void)
{
int i;
char manuf[9];
char device[9];
int design_mv;
if (battery_manufacturer_name(manuf, sizeof(manuf))) {
CPRINTS("Failed to get MANUF name");
return &info_precharge;
}
if (battery_device_name(device, sizeof(device))) {
CPRINTS("Failed to get DEVICE name");
return &info_precharge;
}
if (battery_design_voltage((int *)&design_mv)) {
CPRINTS("Failed to get DESIGN_VOLTAGE");
return &info_precharge;
}
for (i = 0; i < ARRAY_SIZE(support_batteries); ++i) {
if ((strcasecmp(support_batteries[i].manuf, manuf) == 0) &&
(strcasecmp(support_batteries[i].device, device) == 0) &&
(support_batteries[i].design_mv == design_mv)) {
CPRINTS("battery Manuf:%s, Device=%s, design=%u",
manuf, device, design_mv);
support_cut_off = support_batteries[i].support_cut_off;
battery_info = support_batteries[i].battery_info;
return battery_info;
}
}
CPRINTS("un-recognized battery Manuf:%s, Device=%s",
manuf, device);
return &info_precharge;
}
int board_cut_off_battery(void)
{
if (support_cut_off)
return sb_write(SB_SHIP_MODE_ADDR, SB_SHIP_MODE_DATA);
else
return EC_RES_INVALID_COMMAND;
}

49
board/nyan/board.c
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Nyan board-specific configuration */
#include "battery.h"
#include "chipset.h"
#include "common.h"
#include "extpower.h"
#include "gpio.h"
#include "i2c.h"
#include "keyboard_raw.h"
#include "lid_switch.h"
#include "power.h"
#include "power_button.h"
#include "power.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "spi.h"
#include "task.h"
#include "util.h"
#include "timer.h"
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_SOC1V8_XPSHOLD, 1, "XPSHOLD"},
{GPIO_SUSPEND_L, 0, "SUSPEND#_ASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{STM32_TIM(2), STM32_TIM_CH(3),
PWM_CONFIG_ACTIVE_LOW, GPIO_LED_POWER_L},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);

70
board/nyan/board.h
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Nyan board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
#define CONFIG_BATTERY_SMART
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V2
#define CONFIG_CHARGER_BQ24725
#define CONFIG_CHIPSET_TEGRA
#undef CONFIG_CONSOLE_CMDHELP
#define CONFIG_POWER_COMMON
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_HOST_COMMAND_STATUS
#define CONFIG_I2C
#define CONFIG_KEYBOARD_PROTOCOL_MKBP
#define CONFIG_SPI
#define CONFIG_PWM
#define CONFIG_POWER_BUTTON
#define CONFIG_VBOOT_HASH
#ifndef __ASSEMBLER__
/* Keyboard output port list */
#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C
/* Single I2C port, where the EC is the master. */
#define I2C_PORT_MASTER 0
#define I2C_PORT_BATTERY I2C_PORT_MASTER
#define I2C_PORT_CHARGER I2C_PORT_MASTER
/* Timer selection */
#define TIM_CLOCK_MSB 3
#define TIM_CLOCK_LSB 9
#define TIM_POWER_LED 2
#define TIM_WATCHDOG 4
#include "gpio_signal.h"
enum power_signal {
TEGRA_XPSHOLD = 0,
TEGRA_SUSPEND_ASSERTED,
/* Number of power signals */
POWER_SIGNAL_COUNT
};
enum pwm_channel {
PWM_CH_POWER_LED = 0,
/* Number of PWM channels */
PWM_CH_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* Input sensor resistor, mOhm */
#define CONFIG_CHARGER_INPUT_CURRENT 4032 /* mA, based on Link HW design */
#define CONFIG_CHARGER_CURRENT_LIMIT 3000 /* PL102 inductor 3.0A(3.8A) */
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

13
board/nyan/build.mk
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# -*- makefile -*-
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32L100RBT6
CHIP:=stm32
CHIP_FAMILY:=stm32l
CHIP_VARIANT:=stm32l100
board-y=board.o battery.o

24
board/nyan/ec.tasklist
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@@ -1,24 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK(n, r, d, s) where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(POWERLED, power_led_task, NULL, 256) \
TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

62
board/nyan/gpio.inc
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/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(POWER_BUTTON_L, PIN(B, 5), GPIO_INT_BOTH, power_button_interrupt)
GPIO_INT(SOC1V8_XPSHOLD, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt)
GPIO_INT(LID_OPEN, PIN(C, 13), GPIO_INT_BOTH, lid_interrupt)
GPIO_INT(SUSPEND_L, PIN(C, 7), GPIO_KB_INPUT, power_signal_interrupt)
GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_INT_BOTH | GPIO_PULL_UP, spi_event)
GPIO_INT(AC_PRESENT, PIN(A, 0), GPIO_INT_BOTH, extpower_interrupt)
/* Keyboard inputs */
GPIO_INT(KB_IN00, PIN(C, 8), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN01, PIN(C, 9), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN07, PIN(D, 2), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
/* Other inputs */
GPIO(WP_L, PIN(B, 4), GPIO_INPUT)
/* Outputs */
GPIO(AP_RESET_L, PIN(B, 3), GPIO_ODR_HIGH)
GPIO(CHARGER_EN, PIN(B, 2), GPIO_OUT_LOW)
GPIO(EC_INT, PIN(B, 9), GPIO_ODR_HIGH)
GPIO(ENTERING_RW, PIN(H, 0), GPIO_OUT_LOW)
GPIO(I2C1_SCL, PIN(B, 6), GPIO_ODR_HIGH)
GPIO(I2C1_SDA, PIN(B, 7), GPIO_ODR_HIGH)
GPIO(LED_POWER_L, PIN(A, 2), GPIO_OUT_HIGH) /* PWR_LED1 */
GPIO(PMIC_PWRON_L, PIN(A, 12), GPIO_OUT_HIGH)
GPIO(PMIC_RESET, PIN(A, 15), GPIO_OUT_LOW)
GPIO(KB_OUT00, PIN(B, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT01, PIN(B, 8), GPIO_KB_OUTPUT)
GPIO(KB_OUT02, PIN(B, 12), GPIO_KB_OUTPUT)
GPIO(KB_OUT03, PIN(B, 13), GPIO_KB_OUTPUT)
GPIO(KB_OUT04, PIN(B, 14), GPIO_KB_OUTPUT)
GPIO(KB_OUT05, PIN(B, 15), GPIO_KB_OUTPUT)
GPIO(KB_OUT06, PIN(C, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT07, PIN(C, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT08, PIN(C, 2), GPIO_KB_OUTPUT)
GPIO(KB_OUT09, PIN(B, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT10, PIN(C, 5), GPIO_KB_OUTPUT)
GPIO(KB_OUT11, PIN(C, 4), GPIO_KB_OUTPUT)
GPIO(KB_OUT12, PIN(A, 13), GPIO_KB_OUTPUT)
GPIO(PWR_LED0, PIN(B, 10), GPIO_OUT_LOW)
GPIO(BAT_LED0, PIN(B, 11), GPIO_OUT_LOW)
GPIO(BAT_LED1, PIN(A, 8), GPIO_OUT_LOW)
GPIO(CHARGING, PIN(A, 11), GPIO_OUT_LOW)
GPIO(EC_BL_OVERRIDE, PIN(H, 1), GPIO_ODR_HIGH)
GPIO(PMIC_THERM_L, PIN(A, 1), GPIO_ODR_HIGH)
GPIO(PMIC_WARM_RESET_L, PIN(C, 3), GPIO_ODR_HIGH)
ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI, GPIO_DEFAULT)
ALTERNATE(PIN_MASK(A, 0x0600), GPIO_ALT_USART, MODULE_UART, GPIO_DEFAULT)
ALTERNATE(PIN_MASK(B, 0x00c0), GPIO_ALT_I2C, MODULE_I2C, GPIO_DEFAULT)

1
board/peppy/Makefile
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../../Makefile

42
board/peppy/battery.c
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@@ -1,42 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "gpio.h"
#include "host_command.h"
#define SB_SHIP_MODE_ADDR 0x3a
#define SB_SHIP_MODE_DATA 0xc574
/* Values for 54Wh 3UPF656790-1-T1001 battery */
static const struct battery_info info = {
.voltage_max = 12600,
.voltage_normal = 11100, /* Average of max & min */
.voltage_min = 9000,
/* Pre-charge values. */
.precharge_current = 392, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 60,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = 0,
.discharging_max_c = 50,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
return sb_write(SB_SHIP_MODE_ADDR, SB_SHIP_MODE_DATA);
}

134
board/peppy/board.c
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@@ -1,134 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* EC for Peppy board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "backlight.h"
#include "chipset.h"
#include "common.h"
#include "driver/temp_sensor/g781.h"
#include "extpower.h"
#include "fan.h"
#include "gpio.h"
#include "host_command.h"
#include "i2c.h"
#include "jtag.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "peci.h"
#include "power.h"
#include "power_button.h"
#include "registers.h"
#include "switch.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "thermal.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_PP5000_PGOOD, 1, "PGOOD_PP5000"},
{GPIO_PP1350_PGOOD, 1, "PGOOD_PP1350"},
{GPIO_PP1050_PGOOD, 1, "PGOOD_PP1050"},
{GPIO_VCORE_PGOOD, 1, "PGOOD_VCORE"},
{GPIO_PCH_SLP_S0_L, 1, "SLP_S0#_DEASSERTED"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3#_DEASSERTED"},
{GPIO_PCH_SLP_S5_L, 1, "SLP_S5#_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
const struct adc_t adc_channels[] = {
/* EC internal temperature is calculated by
* 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
* = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
*/
{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
/* IOUT == ICMNT is on PE3/AIN0 */
/* We have 0.01-ohm resistors, and IOUT is 20X the differential
* voltage, so 1000mA ==> 200mV.
* ADC returns 0x000-0xFFF, which maps to 0.0-3.3V (as configured).
* mA = 1000 * ADC_VALUE / ADC_READ_MAX * 3300 / 200
*/
{"ChargerCurrent", LM4_ADC_SEQ1, 33000, ADC_READ_MAX * 2, 0,
LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_t fans[] = {
{.flags = FAN_USE_RPM_MODE,
.rpm_min = 1000,
.rpm_start = 1000,
.rpm_max = 5050,
.ch = 2,
.pgood_gpio = GPIO_PP5000_PGOOD,
.enable_gpio = GPIO_PP5000_FAN_EN,
},
};
BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"batt_chg", 0, 100},
{"thermal", 5, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
const struct temp_sensor_t temp_sensors[] = {
{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0, 2},
{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
{"G781Internal", TEMP_SENSOR_TYPE_BOARD, g781_get_val,
G781_IDX_INTERNAL, 4},
{"G781External", TEMP_SENSOR_TYPE_BOARD, g781_get_val,
G781_IDX_EXTERNAL, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
/* Only the AP affects the thermal limits and fan speed. */
{{C_TO_K(95), C_TO_K(97), C_TO_K(99)}, C_TO_K(55), C_TO_K(85)},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
struct keyboard_scan_config keyscan_config = {
.output_settle_us = 40,
.debounce_down_us = 6 * MSEC,
.debounce_up_us = 30 * MSEC,
.scan_period_us = 1500,
.min_post_scan_delay_us = 1000,
.poll_timeout_us = SECOND,
.actual_key_mask = {
0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xca /* full set */
},
};
/**
* Discharge battery when on AC power for factory test.
*/
int board_discharge_on_ac(int enable)
{
if (enable)
gpio_set_level(GPIO_CHARGE_L, 1);
else
gpio_set_level(GPIO_CHARGE_L, 0);
return EC_SUCCESS;
}

116
board/peppy/board.h
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@@ -1,116 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Configuration for Peppy mainboard */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_BACKLIGHT_LID
#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V1
#define CONFIG_CHARGER_BQ24707A
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHIPSET_CAN_THROTTLE
#define CONFIG_CHIPSET_HASWELL
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
#define CONFIG_CMD_GSV
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FANS 1
#define CONFIG_KEYBOARD_BOARD_CONFIG
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_COMMON
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_PECI_TJMAX 100
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_SWITCH_DEDICATED_RECOVERY
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_G781
#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PP3300_DX_EN
#define CONFIG_UART_HOST 2
#define CONFIG_USB_PORT_POWER_DUMB
#define CONFIG_VBOOT_HASH
#define CONFIG_WIRELESS
#ifndef __ASSEMBLER__
/* I2C ports */
#define I2C_PORT_BATTERY 0
#define I2C_PORT_CHARGER 0
#define I2C_PORT_THERMAL 5
/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
#define KB_SCAN_ROW_IRQ LM4_IRQ_GPIOK
#define KB_SCAN_ROW_GPIO LM4_GPIO_K
/* Host connects to keyboard controller module via LPC */
#define HOST_KB_BUS_LPC
/* USB ports */
#define USB_PORT_COUNT 2
#include "gpio_signal.h"
/* power signal definitions */
enum power_signal {
X86_PGOOD_PP5000 = 0,
X86_PGOOD_PP1350,
X86_PGOOD_PP1050,
X86_PGOOD_VCORE,
X86_SLP_S0_DEASSERTED,
X86_SLP_S3_DEASSERTED,
X86_SLP_S5_DEASSERTED,
X86_SLP_SUS_DEASSERTED,
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */
#define CONFIG_CHARGER_INPUT_CURRENT 3078 /* mA, 90% of power supply rating */
enum adc_channel {
/* EC internal die temperature in degrees K. */
ADC_CH_EC_TEMP = 0,
/* Charger current in mA. */
ADC_CH_CHARGER_CURRENT,
ADC_CH_COUNT
};
enum temp_sensor_id {
/* CPU die temperature via PECI */
TEMP_SENSOR_CPU_PECI = 0,
/* EC internal temperature sensor */
TEMP_SENSOR_EC_INTERNAL,
/* G781 internal and external sensors */
TEMP_SENSOR_I2C_G781_INTERNAL,
TEMP_SENSOR_I2C_G781_EXTERNAL,
TEMP_SENSOR_COUNT
};
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
/* Discharge battery when on AC power for factory test. */
int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

12
board/peppy/build.mk
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@@ -1,12 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is TI Stellaris LM4
CHIP:=lm4
board-y=board.o battery.o led.o

27
board/peppy/ec.tasklist
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@@ -1,27 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' is the name of the task
* 'r' is the main routine of the task
* 'd' is an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

101
board/peppy/gpio.inc
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/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(POWER_BUTTON_L, PIN(A, 2), GPIO_INT_BOTH_DSLEEP, power_button_interrupt) /* Power button */
GPIO_INT(LID_OPEN, PIN(A, 3), GPIO_INT_BOTH_DSLEEP, lid_interrupt) /* Lid switch */
GPIO_INT(AC_PRESENT, PIN(H, 3), GPIO_INT_BOTH_DSLEEP, extpower_interrupt) /* AC power present */
GPIO_INT(PCH_BKLTEN, PIN(M, 3), GPIO_INT_BOTH, backlight_interrupt) /* Backlight enable signal from PCH */
GPIO_INT(PCH_SLP_S0_L, PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0# signal from PCH */
GPIO_INT(PCH_SLP_S3_L, PIN(G, 7), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S3# signal from PCH */
GPIO_INT(PCH_SLP_S5_L, PIN(H, 1), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S5# signal from PCH */
GPIO_INT(PCH_SLP_SUS_L, PIN(G, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_SUS# signal from PCH */
GPIO_INT(PP1050_PGOOD, PIN(H, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.05V */
GPIO_INT(PP1350_PGOOD, PIN(H, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.35V (DRAM) */
GPIO_INT(PP5000_PGOOD, PIN(N, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 5V */
GPIO_INT(VCORE_PGOOD, PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on core VR */
GPIO_INT(PCH_EDP_VDD_EN, PIN(J, 1), GPIO_INT_BOTH, power_interrupt) /* PCH wants EDP enabled */
GPIO_INT(RECOVERY_L, PIN(A, 5), GPIO_PULL_UP | GPIO_INT_BOTH, switch_interrupt) /* Recovery signal from servo */
GPIO_INT(WP_L, PIN(A, 4), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */
GPIO_INT(JTAG_TCK, PIN(C, 0), GPIO_DEFAULT, jtag_interrupt) /* JTAG clock input */
GPIO_INT(UART0_RX, PIN(A, 0), GPIO_PULL_UP | GPIO_INT_BOTH_DSLEEP, uart_deepsleep_interrupt) /* UART0 RX input */
/* Other inputs */
GPIO(FAN_ALERT_L, PIN(B, 0), GPIO_INPUT) /* From thermal sensor */
GPIO(PCH_SUSWARN_L, PIN(G, 2), GPIO_INT_BOTH) /* SUSWARN# signal from PCH */
GPIO(USB1_OC_L, PIN(E, 7), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(USB2_OC_L, PIN(E, 0), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(BOARD_VERSION1, PIN(Q, 5), GPIO_INPUT) /* Board version stuffing resistor 1 */
GPIO(BOARD_VERSION2, PIN(Q, 6), GPIO_INPUT) /* Board version stuffing resistor 2 */
GPIO(BOARD_VERSION3, PIN(Q, 7), GPIO_INPUT) /* Board version stuffing resistor 3 */
GPIO(CPU_PGOOD, PIN(C, 4), GPIO_INPUT) /* Power good to the CPU */
GPIO(BAT_PRESENT_L, PIN(B, 4), GPIO_INPUT) /* Battery present. Repurposed BAT_TEMP */
/* Outputs; all unasserted by default except for reset signals */
GPIO(CPU_PROCHOT, PIN(B, 1), GPIO_OUT_LOW) /* Force CPU to think it's overheated */
GPIO(PP1350_EN, PIN(H, 5), GPIO_OUT_LOW) /* Enable 1.35V supply */
GPIO(PP3300_DX_EN, PIN(J, 2), GPIO_OUT_LOW) /* Enable power to lots of peripherals */
GPIO(PP3300_LTE_EN, PIN(D, 2), GPIO_OUT_LOW) /* Enable LTE radio */
GPIO(PP3300_WLAN_EN, PIN(J, 0), GPIO_OUT_LOW) /* Enable WiFi power */
GPIO(SUSP_VR_EN, PIN(C, 7), GPIO_OUT_LOW) /* Enable 1.05V regulator */
GPIO(VCORE_EN, PIN(C, 5), GPIO_OUT_LOW) /* Stuffing option - not connected */
GPIO(PP5000_EN, PIN(H, 7), GPIO_OUT_LOW) /* Enable 5V supply */
GPIO(PP5000_FAN_EN, PIN(J, 3), GPIO_OUT_LOW) /* Enable fan power rail */
GPIO(SYS_PWROK, PIN(H, 2), GPIO_OUT_LOW) /* EC thinks everything is up and ready */
GPIO(WLAN_OFF_L, PIN(J, 4), GPIO_OUT_LOW) /* Disable WiFi radio */
GPIO(CHARGE_L, PIN(E, 6), GPIO_OUT_LOW) /* Allow battery to charge when on AC */
GPIO(ENABLE_BACKLIGHT, PIN(M, 7), GPIO_OUT_LOW) /* Enable backlight power */
GPIO(ENABLE_TOUCHPAD, PIN(N, 1), GPIO_OUT_LOW) /* Enable touchpad power */
GPIO(ENTERING_RW, PIN(D, 3), GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(PCH_DPWROK, PIN(G, 0), GPIO_OUT_LOW) /* Indicate when VccDSW is good */
/*
* HDA_SDO is technically an output, but we need to leave it as an
* input until we drive it high. So can't use open-drain (HI_Z).
*/
GPIO(PCH_HDA_SDO, PIN(G, 1), GPIO_INPUT) /* HDA_SDO signal to PCH; when high, ME ignores security descriptor */
GPIO(PCH_WAKE_L, PIN(F, 0), GPIO_OUT_HIGH) /* Wake signal from EC to PCH */
GPIO(PCH_NMI_L, PIN(F, 2), GPIO_OUT_HIGH) /* Non-maskable interrupt pin to PCH */
GPIO(PCH_PWRBTN_L, PIN(H, 0), GPIO_OUT_HIGH) /* Power button output to PCH */
GPIO(PCH_PWROK, PIN(F, 5), GPIO_OUT_LOW) /* PWROK / APWROK signals to PCH */
/*
* PL6 is one of 4 pins on the EC which can't be used in open-drain
* mode. To work around this PCH_RCIN_L is set to an input. It will
* only be set to an output when it needs to be driven to 0.
*/
GPIO(PCH_RCIN_L, PIN(L, 6), GPIO_INPUT) /* RCIN# line to PCH (for 8042 emulation) */
GPIO(PCH_RSMRST_L, PIN(F, 1), GPIO_OUT_LOW) /* Reset PCH resume power plane logic */
GPIO(PCH_SMI_L, PIN(F, 4), GPIO_ODR_HIGH) /* System management interrupt to PCH */
GPIO(TOUCHSCREEN_RESET_L, PIN(N, 7), GPIO_OUT_LOW) /* Reset touch screen */
GPIO(EC_EDP_VDD_EN, PIN(J, 5), GPIO_OUT_LOW) /* Enable EDP (passthru from PCH) */
GPIO(LPC_CLKRUN_L, PIN(M, 2), GPIO_ODR_HIGH) /* Dunno. Probably important, though. */
GPIO(USB1_ENABLE, PIN(E, 4), GPIO_OUT_LOW) /* USB port 1 output power enable */
GPIO(USB2_ENABLE, PIN(D, 5), GPIO_OUT_LOW) /* USB port 2 output power enable */
GPIO(PCH_SUSACK_L, PIN(F, 3), GPIO_OUT_HIGH) /* Acknowledge PCH SUSWARN# signal */
GPIO(PCH_RTCRST_L, PIN(F, 6), GPIO_ODR_HIGH) /* Not supposed to be here */
GPIO(PCH_SRTCRST_L, PIN(F, 7), GPIO_ODR_HIGH) /* Not supposed to be here */
GPIO(BAT_LED0_L, PIN(D, 0), GPIO_ODR_HIGH) /* Battery charging LED - blue */
GPIO(BAT_LED1_L, PIN(N, 4), GPIO_ODR_HIGH) /* Battery charging LED - orange */
GPIO(PWR_LED0_L, PIN(D, 1), GPIO_ODR_HIGH) /* Power LED - blue */
GPIO(PWR_LED1_L, PIN(N, 6), GPIO_ODR_HIGH) /* Power LED - orange */
ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART0 */
ALTERNATE(PIN_MASK(B, 0x04), 3, MODULE_I2C, 0) /* I2C0 SCL */
ALTERNATE(PIN_MASK(B, 0x08), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C0 SDA */
ALTERNATE(PIN_MASK(B, 0x40), 3, MODULE_I2C, 0) /* I2C5 SCL */
ALTERNATE(PIN_MASK(B, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C5 SDA */
ALTERNATE(PIN_MASK(G, 0x30), 1, MODULE_UART, 0) /* UART2 */
ALTERNATE(PIN_MASK(J, 0x40), 1, MODULE_PECI, 0) /* PECI Tx */
ALTERNATE(PIN_MASK(J, 0x80), 0, MODULE_PECI, GPIO_ANALOG) /* PECI Rx */
ALTERNATE(PIN_MASK(L, 0x3f), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(M, 0x33), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(N, 0x0c), 1, MODULE_PWM_FAN, 0) /* FAN0PWM2 */

186
board/peppy/led.c
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/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control for Peppy.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "led_common.h"
#include "util.h"
#define LED_TOTAL_TICKS 16
#define LED_ON_TICKS 4
enum led_color {
LED_OFF = 0,
LED_BLUE,
LED_AMBER,
LED_PINK,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
static int peppy_led_set_gpio(enum led_color color,
enum gpio_signal gpio_led_blue_l,
enum gpio_signal gpio_led_amber_l)
{
switch (color) {
case LED_OFF:
gpio_set_level(gpio_led_blue_l, 1);
gpio_set_level(gpio_led_amber_l, 1);
break;
case LED_BLUE:
gpio_set_level(gpio_led_blue_l, 0);
gpio_set_level(gpio_led_amber_l, 1);
break;
case LED_AMBER:
gpio_set_level(gpio_led_blue_l, 1);
gpio_set_level(gpio_led_amber_l, 0);
break;
case LED_PINK:
gpio_set_level(gpio_led_blue_l, 0);
gpio_set_level(gpio_led_amber_l, 0);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
static int peppy_led_set_color_battery(enum led_color color)
{
return peppy_led_set_gpio(color, GPIO_BAT_LED0_L, GPIO_BAT_LED1_L);
}
static int peppy_led_set_color_power(enum led_color color)
{
return peppy_led_set_gpio(color, GPIO_PWR_LED0_L, GPIO_PWR_LED1_L);
}
static int peppy_led_set_color(enum ec_led_id led_id, enum led_color color)
{
int rv;
led_auto_control(led_id, 0);
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
rv = peppy_led_set_color_battery(color);
break;
case EC_LED_ID_POWER_LED:
rv = peppy_led_set_color_power(color);
break;
default:
return EC_ERROR_UNKNOWN;
}
return rv;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
if (brightness[EC_LED_COLOR_BLUE] != 0 &&
brightness[EC_LED_COLOR_YELLOW] != 0)
peppy_led_set_color(led_id, LED_PINK);
else if (brightness[EC_LED_COLOR_BLUE] != 0)
peppy_led_set_color(led_id, LED_BLUE);
else if (brightness[EC_LED_COLOR_YELLOW] != 0)
peppy_led_set_color(led_id, LED_AMBER);
else
peppy_led_set_color(led_id, LED_OFF);
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
/* Ignoring led_id as both leds support the same colors */
brightness_range[EC_LED_COLOR_BLUE] = 1;
brightness_range[EC_LED_COLOR_YELLOW] = 1;
}
static void peppy_led_set_power(void)
{
static int power_ticks;
static int previous_state_suspend;
power_ticks++;
if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
/* Reset ticks if entering suspend so LED turns amber
* as soon as possible. */
if (!previous_state_suspend)
power_ticks = 0;
/* Blink once every four seconds. */
peppy_led_set_color_power(
(power_ticks % LED_TOTAL_TICKS < LED_ON_TICKS) ?
LED_AMBER : LED_OFF);
previous_state_suspend = 1;
return;
}
previous_state_suspend = 0;
if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
peppy_led_set_color_power(LED_OFF);
else if (chipset_in_state(CHIPSET_STATE_ON))
peppy_led_set_color_power(LED_BLUE);
}
static void peppy_led_set_battery(void)
{
static int battery_ticks;
uint32_t chflags = charge_get_flags();
battery_ticks++;
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
peppy_led_set_color_battery(LED_AMBER);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
peppy_led_set_color_battery(LED_BLUE);
break;
case PWR_STATE_DISCHARGE:
peppy_led_set_color_battery(LED_OFF);
break;
case PWR_STATE_ERROR:
peppy_led_set_color_battery(
(battery_ticks % LED_TOTAL_TICKS < LED_ON_TICKS) ?
LED_AMBER : LED_OFF);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE. */
if (chflags & CHARGE_FLAG_FORCE_IDLE)
peppy_led_set_color_battery(
(battery_ticks & 0x4) ? LED_BLUE : LED_OFF);
else
peppy_led_set_color_battery(LED_BLUE);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/* Called by hook task every 250mSec */
static void led_tick(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
peppy_led_set_power();
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
peppy_led_set_battery();
}
DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);

1
board/snow/Makefile
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../../Makefile

202
board/snow/board.c
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@@ -1,202 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Snow board-specific configuration */
#include "battery.h"
#include "board_config.h"
#include "chipset.h"
#include "common.h"
#include "console.h"
#include "gpio.h"
#include "hooks.h"
#include "i2c.h"
#include "keyboard_raw.h"
#include "lid_switch.h"
#include "pmu_tpschrome.h"
#include "power.h"
#include "power_led.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "spi.h"
#include "task.h"
#include "timer.h"
#include "util.h"
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
#define INT_BOTH_FLOATING (GPIO_INPUT | GPIO_INT_BOTH)
#define INT_BOTH_PULL_UP (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#include "gpio_list.h"
/* Battery temperature ranges in degrees C */
static const struct battery_info info = {
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = 0,
.discharging_max_c = 100,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100, GPIO_I2C1_SCL, GPIO_I2C1_SDA},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{STM32_TIM(2), STM32_TIM_CH(2),
PWM_CONFIG_ACTIVE_LOW, GPIO_LED_POWER_L},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
void board_config_pre_init(void)
{
uint32_t val;
/* Enable all GPIOs clocks */
STM32_RCC_APB2ENR |= 0x1fd;
/* remap OSC_IN/OSC_OUT to PD0/PD1 */
STM32_GPIO_AFIO_MAPR |= 1 << 15;
/* use PB3 as a GPIO, so disable JTAG and keep only SWD */
STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x7 << 24))
| (2 << 24);
/* remap TIM2_CH2 to PB3 */
STM32_GPIO_AFIO_MAPR = (STM32_GPIO_AFIO_MAPR & ~(0x3 << 8))
| (1 << 8);
/*
* Set alternate function for USART1. For alt. function input
* the port is configured in either floating or pull-up/down
* input mode (ref. section 7.1.4 in datasheet RM0041):
* PA9: Tx, alt. function output
* PA10: Rx, input with pull-down
*
* note: see crosbug.com/p/12223 for more info
*/
val = STM32_GPIO_CRH(GPIO_A) & ~0x00000ff0;
val |= 0x00000890;
STM32_GPIO_CRH(GPIO_A) = val;
/* EC_INT is output, open-drain */
val = STM32_GPIO_CRH(GPIO_B) & ~0xf0;
val |= 0x50;
STM32_GPIO_CRH(GPIO_B) = val;
/* put GPIO in Hi-Z state */
gpio_set_level(GPIO_EC_INT, 1);
}
/* GPIO configuration to be done after I2C module init */
void board_i2c_post_init(int port)
{
uint32_t val;
/* enable alt. function (open-drain) */
if (port == STM32_I2C1_PORT) {
/* I2C1 is on PB6-7 */
val = STM32_GPIO_CRL(GPIO_B) & ~0xff000000;
val |= 0xdd000000;
STM32_GPIO_CRL(GPIO_B) = val;
} else if (port == STM32_I2C2_PORT) {
/* I2C2 is on PB10-11 */
val = STM32_GPIO_CRH(GPIO_B) & ~0x0000ff00;
val |= 0x0000dd00;
STM32_GPIO_CRH(GPIO_B) = val;
}
}
void keyboard_suppress_noise(void)
{
/* notify audio codec of keypress for noise suppression */
gpio_set_level(GPIO_CODEC_INT, 0);
gpio_set_level(GPIO_CODEC_INT, 1);
}
static void board_startup_hook(void)
{
gpio_set_flags(GPIO_SUSPEND_L, INT_BOTH_PULL_UP);
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, board_startup_hook, HOOK_PRIO_DEFAULT);
static void board_shutdown_hook(void)
{
/* Disable pull-up on SUSPEND_L during shutdown to prevent leakage */
gpio_set_flags(GPIO_SUSPEND_L, INT_BOTH_FLOATING);
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, board_shutdown_hook, HOOK_PRIO_DEFAULT);
int pmu_board_init(void)
{
int ver, failure = 0;
/* Set fast charging timeout to 6 hours*/
if (!failure)
failure = pmu_set_fastcharge(TIMEOUT_6HRS);
/* Enable external gpio CHARGER_EN control */
if (!failure)
failure = pmu_enable_ext_control(1);
/* Disable force charging */
if (!failure)
failure = pmu_enable_charger(0);
/* Set NOITERM bit */
if (!failure)
failure = pmu_low_current_charging(1);
/*
* High temperature charging
* termination voltage: 2.1V
* termination current: 100%
*/
if (!failure)
failure = pmu_set_term_voltage(RANGE_T34, TERM_V2100);
if (!failure)
failure = pmu_set_term_current(RANGE_T34, TERM_I1000);
/*
* Standard temperature charging
* termination voltage: 2.1V
* termination current: 100%
*/
if (!failure)
failure = pmu_set_term_voltage(RANGE_T23, TERM_V2100);
if (!failure)
failure = pmu_set_term_current(RANGE_T23, TERM_I1000);
/*
* Ignore TPSCHROME NTC reading in T40. This is snow board specific
* setting. Check:
* http://crosbug.com/p/12221
* http://crosbug.com/p/13171
*/
if (!failure)
failure = pmu_set_term_voltage(RANGE_T40, TERM_V2100);
if (!failure)
failure = pmu_set_term_current(RANGE_T40, TERM_I1000);
/* Workaround init values before ES3 */
if (pmu_version(&ver) || ver < 3) {
/* Termination current: 75% */
if (!failure)
failure = pmu_set_term_current(RANGE_T34, TERM_I0750);
if (!failure)
failure = pmu_set_term_current(RANGE_T23, TERM_I0750);
if (!failure)
failure = pmu_set_term_current(RANGE_T40, TERM_I0750);
}
return failure ? EC_ERROR_UNKNOWN : EC_SUCCESS;
}

68
board/snow/board.h
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@@ -1,68 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Snow board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* 16 MHz SYSCLK clock frequency */
#define CPU_CLOCK 16000000
/* Debug features */
#undef CONFIG_TASK_PROFILING
/* Optional features */
#define CONFIG_BATTERY_BQ20Z453
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_CHARGER_TPS65090
#define CONFIG_CHIPSET_GAIA
#define CONFIG_CMD_PMU
#define CONFIG_EXTPOWER_SNOW
#define CONFIG_HOST_COMMAND_STATUS
#define CONFIG_I2C
#define CONFIG_I2C_ARBITRATION
#define CONFIG_KEYBOARD_PROTOCOL_MKBP
#define CONFIG_KEYBOARD_SUPPRESS_NOISE
#define CONFIG_PMU_HARD_RESET
#define CONFIG_PMU_TPS65090
#define CONFIG_PWM
#define CONFIG_VBOOT_HASH
/* use STOP mode when we have nothing to do */
#define CONFIG_LOW_POWER_IDLE
#ifndef __ASSEMBLER__
/* Keyboard output ports */
#define KB_OUT_PORT_LIST GPIO_B, GPIO_C
/* Charging */
#define I2C_PORT_MASTER 1
#define I2C_PORT_BATTERY I2C_PORT_MASTER
#define I2C_PORT_CHARGER I2C_PORT_MASTER
#define I2C_PORT_SLAVE 1
#define GPIO_AP_CLAIM GPIO_SPI1_NSS /* AP claims bus */
#define GPIO_EC_CLAIM GPIO_SPI1_MISO /* EC claims bus */
/* Timer selection */
#define TIM_CLOCK_MSB 3
#define TIM_CLOCK_LSB 4
#define TIM_POWER_LED 2
#define TIM_WATCHDOG 1
#include "gpio_signal.h"
enum pwm_channel {
PWM_CH_POWER_LED = 0,
/* Number of PWM channels */
PWM_CH_COUNT
};
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

13
board/snow/build.mk
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@@ -1,13 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F100RB
CHIP:=stm32
CHIP_FAMILY:=stm32f
CHIP_VARIANT:=stm32f100
board-y=board.o

26
board/snow/ec.tasklist
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@@ -1,26 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' in the name of the task
* 'r' in the main routine of the task
* 'd' in an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_NOTEST(POWERLED, power_led_task, NULL, 256) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, 360)

70
board/snow/gpio.inc
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@@ -1,70 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Inputs with interrupt handlers are first for efficiency */
GPIO_INT(KB_PWR_ON_L, PIN(B, 5), GPIO_INT_BOTH, power_signal_interrupt) /* Keyboard power button */
GPIO_INT(PP1800_LDO2, PIN(A, 1), GPIO_INT_BOTH, power_signal_interrupt) /* LDO2 is ON (end of PMIC sequence) */
GPIO_INT(SOC1V8_XPSHOLD, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) /* App Processor ON */
GPIO_INT(CHARGER_INT_L, PIN(C, 4), GPIO_INT_FALLING, pmu_irq_handler)
GPIO_INT(LID_OPEN, PIN(C, 13), GPIO_INT_BOTH, lid_interrupt) /* LID switch detection */
GPIO_INT(SUSPEND_L, PIN(A, 7), INT_BOTH_FLOATING, power_signal_interrupt) /* AP suspend/resume state */
GPIO_INT(SPI1_NSS, PIN(A, 4), GPIO_DEFAULT, spi_event)
/* Keyboard inputs */
GPIO_INT(KB_IN00, PIN(C, 8), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN01, PIN(C, 9), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN02, PIN(C, 10), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN03, PIN(C, 11), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN04, PIN(C, 12), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN05, PIN(C, 14), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN06, PIN(C, 15), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
GPIO_INT(KB_IN07, PIN(D, 2), GPIO_KB_INPUT, keyboard_raw_gpio_interrupt)
/* Other inputs */
GPIO(AC_PWRBTN_L, PIN(A, 0), GPIO_INT_BOTH)
GPIO(WP_L, PIN(B, 4), GPIO_INPUT) /* Write protection pin (low active) */
/*
* I2C pins should be configured as inputs until I2C module is
* initialized. This will avoid driving the lines unintentionally.
*/
GPIO(I2C1_SCL, PIN(B, 6), GPIO_INPUT)
GPIO(I2C1_SDA, PIN(B, 7), GPIO_INPUT)
GPIO(I2C2_SCL, PIN(B, 10), GPIO_INPUT)
GPIO(I2C2_SDA, PIN(B, 11), GPIO_INPUT)
/* Outputs */
GPIO(AC_STATUS, PIN(A, 5), GPIO_DEFAULT)
GPIO(SPI1_MISO, PIN(A, 6), GPIO_DEFAULT)
GPIO(EN_PP1350, PIN(A, 2), GPIO_OUT_LOW) /* DDR 1.35v rail enable */
GPIO(EN_PP5000, PIN(A, 11), GPIO_OUT_LOW) /* 5.0v rail enable */
GPIO(EN_PP3300, PIN(A, 8), GPIO_OUT_LOW) /* 3.3v rail enable */
GPIO(PMIC_PWRON_L,PIN(A, 12), GPIO_OUT_HIGH) /* 5v rail ready */
GPIO(PMIC_RESET, PIN(A, 15), GPIO_OUT_LOW) /* Force hard reset of the pmic */
/* EC is R/W mode for the kbc mux */
GPIO(ENTERING_RW, PIN(D, 0), GPIO_OUT_LOW)
GPIO(CHARGER_EN, PIN(B, 2), GPIO_OUT_LOW)
GPIO(EC_INT, PIN(B, 9), GPIO_ODR_HIGH)
/* To audio codec (KB noise cancellation) */
GPIO(CODEC_INT, PIN(D, 1), GPIO_ODR_HIGH)
GPIO(LED_POWER_L, PIN(B, 3), GPIO_INPUT) /* Keyboard power LED */
GPIO(KB_OUT00, PIN(B, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT01, PIN(B, 8), GPIO_KB_OUTPUT)
GPIO(KB_OUT02, PIN(B, 12), GPIO_KB_OUTPUT)
GPIO(KB_OUT03, PIN(B, 13), GPIO_KB_OUTPUT)
GPIO(KB_OUT04, PIN(B, 14), GPIO_KB_OUTPUT)
GPIO(KB_OUT05, PIN(B, 15), GPIO_KB_OUTPUT)
GPIO(KB_OUT06, PIN(C, 0), GPIO_KB_OUTPUT)
GPIO(KB_OUT07, PIN(C, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT08, PIN(C, 2), GPIO_KB_OUTPUT)
GPIO(KB_OUT09, PIN(B, 1), GPIO_KB_OUTPUT)
GPIO(KB_OUT10, PIN(C, 5), GPIO_KB_OUTPUT)
GPIO(KB_OUT11, PIN(C, 6), GPIO_KB_OUTPUT)
GPIO(KB_OUT12, PIN(C, 7), GPIO_KB_OUTPUT)

1
board/speedy/Makefile
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../../Makefile

54
board/speedy/battery.c
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/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "console.h"
#include "gpio.h"
#include "host_command.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHUTDOWN_DATA 0x0010
static const struct battery_info info = {
.voltage_max = 8400, /* mV */
.voltage_normal = 7400,
.voltage_min = 6000,
.precharge_current = 256, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 45,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
static int cutoff(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
}
int board_cut_off_battery(void)
{
return cutoff();
}

75
board/speedy/board.c
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Veyron board-specific configuration */
#include "battery.h"
#include "chipset.h"
#include "common.h"
#include "extpower.h"
#include "gpio.h"
#include "i2c.h"
#include "keyboard_raw.h"
#include "lid_switch.h"
#include "power.h"
#include "power_button.h"
#include "power.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "spi.h"
#include "task.h"
#include "util.h"
#include "timer.h"
#include "charger.h"
#define GPIO_KB_INPUT (GPIO_INPUT | GPIO_PULL_UP | GPIO_INT_BOTH)
#define GPIO_KB_OUTPUT GPIO_ODR_HIGH
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_SOC_POWER_GOOD, 1, "POWER_GOOD"},
{GPIO_SUSPEND_L, 1, "SUSPEND#_ASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"master", I2C_PORT_MASTER, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{STM32_TIM(2), STM32_TIM_CH(3),
PWM_CONFIG_ACTIVE_LOW},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
/**
* Discharge battery when on AC power for factory test.
*/
int board_discharge_on_ac(int enable)
{
return charger_discharge_on_ac(enable);
}
void board_config_pre_init(void)
{
/* enable SYSCFG clock */
STM32_RCC_APB2ENR |= 1 << 0;
/* Remap USART DMA to match the USART driver */
/*
* the DMA mapping is :
* Chan 2 : TIM1_CH1
* Chan 3 : SPI1_TX
* Chan 4 : USART1_TX
* Chan 5 : USART1_RX
*/
STM32_SYSCFG_CFGR1 |= (1 << 9) | (1 << 10); /* Remap USART1 RX/TX DMA */
}

88
board/speedy/board.h
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/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Veyron board configuration */
#ifndef __BOARD_H
#define __BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_PRE_INIT
#define CONFIG_CHARGER
#define CONFIG_CHARGER_BQ24715
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_V2
#define CONFIG_CHIPSET_ROCKCHIP
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FORCE_CONSOLE_RESUME
#define CONFIG_HOST_COMMAND_STATUS
#define CONFIG_I2C
#define CONFIG_KEYBOARD_COL2_INVERTED
#define CONFIG_KEYBOARD_PROTOCOL_MKBP
#define CONFIG_LED_COMMON
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_LOW_POWER_S0
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_ACTIVE_STATE 1
#define CONFIG_POWER_COMMON
#define CONFIG_PWM
#define CONFIG_SPI
#define CONFIG_STM_HWTIMER32
#define CONFIG_UART_RX_DMA
#define CONFIG_VBOOT_HASH
#undef CONFIG_WATCHDOG_HELP
#define CONFIG_HIBERNATE_WAKEUP_PINS (STM32_PWR_CSR_EWUP1 | STM32_PWR_CSR_EWUP6)
#ifndef __ASSEMBLER__
/* 48 MHz SYSCLK clock frequency */
#define CPU_CLOCK 48000000
/* Keyboard output port list */
#define KB_OUT_PORT_LIST GPIO_A, GPIO_B, GPIO_C
/* Single I2C port, where the EC is the master. */
#define I2C_PORT_MASTER 0
#define I2C_PORT_BATTERY I2C_PORT_MASTER
#define I2C_PORT_CHARGER I2C_PORT_MASTER
/* Timer selection */
#define TIM_CLOCK32 2
#define TIM_WATCHDOG 4
#include "gpio_signal.h"
enum power_signal {
RK_POWER_GOOD = 0,
RK_SUSPEND_ASSERTED,
/* Number of power signals */
POWER_SIGNAL_COUNT
};
enum pwm_channel {
PWM_CH_POWER_LED = 0,
/* Number of PWM channels */
PWM_CH_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20 /* Input sensor resistor, mOhm */
/* Input current limit for 45W AC adapter:
* 45W/19V*85%=2013mA, choose the closest charger setting = 2048mA
*/
#define CONFIG_CHARGER_INPUT_CURRENT 2048 /* mA, based on Link HW design */
#define CONFIG_CHARGER_CURRENT_LIMIT 3000 /* PL102 inductor 3.0A(3.8A) */
/* Discharge battery when on AC power for factory test. */
int board_discharge_on_ac(int enable);
#endif /* !__ASSEMBLER__ */
#endif /* __BOARD_H */

13
board/speedy/build.mk
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# -*- makefile -*-
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
# the IC is STmicro STM32F071RB
CHIP:=stm32
CHIP_FAMILY:=stm32f0
CHIP_VARIANT:=stm32f07x
board-y=board.o battery.o led.o

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