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baytrail: Rearrange config options alphanumerically

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This is a no-op change for easier maintenance.

BUG=none
TEST=manual
    . baitrail coreboot still builds and runs

Change-Id: I0c0bd78c6f361e8f81979f19cce148e7f51865ee
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/171002
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4857
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Vadim Bendebury
2013-09-27 16:21:04 -07:00
committed by Aaron Durbin
parent 794bddf97c
commit c04e171467
1 changed files with 16 additions and 15 deletions
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31
src/soc/intel/baytrail/Kconfig
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@@ -8,24 +8,25 @@ if SOC_INTEL_BAYTRAIL
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMP
select SSE2
select UDELAY_TSC
select TSC_CONSTANT_RATE
select SMM_TSEG
select SMM_MODULES
select RELOCATABLE_MODULES
select DYNAMIC_CBMEM
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_SYNC_MFENCE
select CAR_MIGRATION
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select HAVE_SMI_HANDLER
select CACHE_MRC_SETTINGS
select CACHE_ROM
select SPI_FLASH
select CAR_MIGRATION
select COLLECT_TIMESTAMPS
select CPU_MICROCODE_IN_CBFS
select DYNAMIC_CBMEM
select HAVE_SMI_HANDLER
select MMCONF_SUPPORT
select MMCONF_SUPPORT_DEFAULT
select RELOCATABLE_MODULES
select SMM_MODULES
select SMM_TSEG
select SMP
select SPI_FLASH
select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_CONSTANT_RATE
select TSC_SYNC_MFENCE
select UDELAY_TSC
config BOOTBLOCK_CPU_INIT
string