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ISH: correction for HPET1 interrupt routing

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-Routing HPET1 timer requires HPET's General Config register's Legacy
routing bit should be set.
-For HPET0 interrupt, no need to set IRQ# to T0C register.
-change IRQ# back to default values.

BUG=None
BRANCH=master
TEST=`Build ISH and verify the timer interrupt via various
      console cmds`

Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/627628
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyoung Kim
2017-08-22 15:29:55 -07:00
committed by chrome-bot
parent f35ae8ab1c
commit c07c76e9ca
3 changed files with 10 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
chip/ish/hpet.h
View File

@@ -33,6 +33,8 @@
#define HPET_T_CONF_CAP_BIT 0x4
#define HPET_ENABLE_CNF (1<<0)
#define HPET_LEGACY_RT_CNF (1<<1)
#define HPET_Tn_INT_TYPE_CNF (1<<1)
#define HPET_Tn_INT_ENB_CNF (1<<2)
#define HPET_Tn_TYPE_CNF (1<<3)

11
chip/ish/hwtimer.c
View File

@@ -98,10 +98,8 @@ int __hw_clock_source_init(uint32_t start_t)
timer0_config |= HPET_Tn_32MODE_CNF;
timer0_config |= HPET_Tn_VAL_SET_CNF;
/* Timer 0 - IRQ routing */
/* Timer 0 - IRQ routing, no need IRQ set for HPET0 */
timer0_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
timer0_config |= (ISH_HPET_TIMER0_IRQ <<
HPET_Tn_INT_ROUTE_CNF_SHIFT);
/* Timer 1 - IRQ routing */
timer1_config &= ~HPET_Tn_INT_ROUTE_CNF_MASK;
@@ -130,8 +128,11 @@ int __hw_clock_source_init(uint32_t start_t)
;
#endif
/* Enable HPET main counter */
HPET_GENERAL_CONFIG |= HPET_ENABLE_CNF;
/*
* LEGACY_RT_CNF for HPET1 interrupt routing
* and enable overall HPET counter/interrupts.
*/
HPET_GENERAL_CONFIG |= (HPET_ENABLE_CNF | HPET_LEGACY_RT_CNF);
return ISH_HPET_TIMER1_IRQ;
}

4
chip/ish/registers.h
View File

@@ -39,8 +39,8 @@ enum ish_i2c_port {
/* HW interrupt pins mapped to IOAPIC, from I/O sources */
#define ISH_I2C0_IRQ 0
#define ISH_I2C1_IRQ 1
#define ISH_HPET_TIMER0_IRQ 22
#define ISH_HPET_TIMER1_IRQ 23
#define ISH_HPET_TIMER0_IRQ 55
#define ISH_HPET_TIMER1_IRQ 8
#define ISH_HPET_TIMER2_IRQ 11
#define ISH_IPC_HOST2ISH_IRQ 12
#define ISH_IPC_ISH2HOST_CLR_IRQ 24