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oak: stm32f0: implement i2c_set_timeout

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EC communicates with PD through I2C host command. This CL adds
i2c_set_timeout implementation.

BRANCH=none
BUG=chrome-os-partner:41608
TEST=manual
  build and load on oak, check PD host command.

Change-Id: I05259b40223b435eaf2a0c38954573e97ea4b32b
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/306909
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Rong Chang
2015-10-20 14:27:17 +08:00
committed by chrome-bot
parent d8b81cdc0f
commit c5f9f00dfb
2 changed files with 16 additions and 8 deletions
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7
board/oak/board.c
View File

@@ -189,13 +189,6 @@ void pd_send_host_event(int mask)
host_set_single_event(EC_HOST_EVENT_PD_MCU);
}
void __board_i2c_set_timeout(int port, uint32_t timeout)
{
}
void i2c_set_timeout(int port, uint32_t timeout)
__attribute__((weak, alias("__board_i2c_set_timeout")));
/**
* There is a level shift for AC_OK & LID_OPEN signal between AP & EC,
* disable it (drive high) when AP is off, otherwise enable it (drive low).

17
chip/stm32/i2c-stm32f0.c
View File

@@ -40,6 +40,18 @@
#endif
#endif
/* I2C port state data */
struct i2c_port_data {
uint32_t timeout_us; /* Transaction timeout, or 0 to use default */
};
static struct i2c_port_data pdata[I2C_PORT_COUNT];
void i2c_set_timeout(int port, uint32_t timeout)
{
pdata[port].timeout_us = timeout ? timeout : I2C_TX_TIMEOUT_MASTER;
}
/**
* Wait for ISR register to contain the specified mask.
*
@@ -48,7 +60,7 @@
*/
static int wait_isr(int port, int mask)
{
uint64_t timeout = get_time().val + I2C_TX_TIMEOUT_MASTER;
uint64_t timeout = get_time().val + pdata[port].timeout_us;
while (get_time().val < timeout) {
int isr = STM32_I2C_ISR(port);
@@ -143,6 +155,9 @@ defined(CONFIG_LOW_POWER_IDLE) && \
/* Set up initial bus frequencies */
i2c_set_freq_port(p);
/* Set up default timeout */
i2c_set_timeout(port, 0);
}
/*****************************************************************************/