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Stay in G3 when power applied

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We were going straight to S5.  When the PCH first goes into S5 after
power-loss, it decides to boot for some reason.  So, stay in G3.

Still exit G3 if waking from hibernate or if the power button is
pressed when the EC boots on a power-on reset.

BUG=chrome-os-partner:10239
TEST=manual

1) Unplug battery and AC power.  Plug in AC power.  System does not boot.
2) Press power button.  System boots now.
3) From console, 'hibernate 10'.  Close and open lid.  System boots.
4) From console, 'hibernate 10'.  Press power button.  System boots.
5) Hold power+esc+refresh.  System boots into recovery.
6) Hold power+esc.  EC reboots.  Release esc.  System stays off.
7) Unplug battery and AC power.  Plug in AC power while holding power button.
   System boots.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

Change-Id: I7612a40ab5ebe41d356ac3a6b89cedf1174125f4
Reviewed-on: https://gerrit.chromium.org/gerrit/24729
Commit-Ready: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Randall Spangler
2012-06-07 09:51:29 -07:00
committed by Gerrit
parent d9c385da74
commit c8eb271d6a
2 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
chip/lm4/power_button.c
View File

@@ -308,6 +308,7 @@ static void set_initial_pwrbtn_state(void)
/* In recovery mode, so send a power button pulse to
* the PCH so it powers on. */
CPRINTF("[%T PB init-recovery]\n");
chipset_exit_hard_off();
set_pwrbtn_to_pch(0);
pwrbtn_state = PWRBTN_STATE_BOOT_RECOVERY;
tnext_state = get_time().val + PWRBTN_INITIAL_US;
@@ -328,6 +329,7 @@ static void set_initial_pwrbtn_state(void)
* system. Note that on EVT+, if the system is off, lid is
* open, and you plug it in, it'll turn on due to AC detect. */
CPRINTF("[%T PB init-hib-wake]\n");
chipset_exit_hard_off();
set_pwrbtn_to_pch(0);
if (get_power_button_pressed())
pwrbtn_state = PWRBTN_STATE_WAS_OFF;
@@ -338,8 +340,11 @@ static void set_initial_pwrbtn_state(void)
/* Copy initial power button state to PCH and memory-mapped
* switch positions. */
set_pwrbtn_to_pch(get_power_button_pressed() ? 0 : 1);
if (get_power_button_pressed())
if (get_power_button_pressed()) {
/* Wake chipset if power button is pressed at boot */
chipset_exit_hard_off();
*memmap_switches |= EC_SWITCH_POWER_BUTTON_PRESSED;
}
}
}

11
common/x86_power.c
View File

@@ -91,7 +91,7 @@ static const char * const state_names[] = {
#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE | \
IN_PGOOD_CPU_CORE | IN_ALL_PM_SLP_DEASSERTED)
static enum x86_state state; /* Current state */
static enum x86_state state = X86_G3; /* Current state */
static uint32_t in_signals; /* Current input signal states (IN_PGOOD_*) */
static uint32_t in_want; /* Input signal state we're waiting for */
static int want_g3_exit; /* Should we exit the G3 state? */
@@ -264,7 +264,9 @@ void chipset_exit_hard_off(void)
/* Set a flag to leave G3, then wake the task */
want_g3_exit = 1;
task_wake(TASK_ID_X86POWER);
if (task_start_called())
task_wake(TASK_ID_X86POWER);
}
@@ -322,11 +324,6 @@ void x86_power_interrupt(enum gpio_signal signal)
static int x86_power_init(void)
{
/* Default to moving towards S5 state unless proven otherwise. This
* supports booting the main processor during the boot process. We'll
* drop back to G3 if we stay inactive in S5.*/
state = X86_G3S5;
/* Update input state */
update_in_signals();
in_want = 0;