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ec: delete auron and rambi boards

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These boards have been succeeded by newer boards.

BUG=chromium:686106
TEST=make -j buildall
CQ-DEPEND=CL:434909
BRANCH=none

Change-Id: I2c964c1fdd7f8bbc5dab07caa88864847ba4e312
Reviewed-on: https://chromium-review.googlesource.com/434540
Commit-Ready: Sam Hurst <shurst@google.com>
Tested-by: Sam Hurst <shurst@google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Sam Hurst
2017-01-30 07:48:17 -08:00
committed by chrome-bot
parent bf557f235a
commit ca0d5aba6b
19 changed files with 0 additions and 1959 deletions
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42
board/auron/battery.c
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@@ -1,42 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "gpio.h"
#include "host_command.h"
#define SB_SHIP_MODE_ADDR 0x3a
#define SB_SHIP_MODE_DATA 0xc574
/* Values for 54Wh 3UPF656790-1-T1001 battery */
static const struct battery_info info = {
.voltage_max = 12600,
.voltage_normal = 11100, /* Average of max & min */
.voltage_min = 9000,
/* Pre-charge values. */
.precharge_current = 392, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 60,
.charging_min_c = 0,
.charging_max_c = 60,
.discharging_min_c = 0,
.discharging_max_c = 50,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
return sb_write(SB_SHIP_MODE_ADDR, SB_SHIP_MODE_DATA);
}

134
board/auron/board.c
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@@ -1,134 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* EC for Auron board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "backlight.h"
#include "chipset.h"
#include "common.h"
#include "driver/temp_sensor/g78x.h"
#include "extpower.h"
#include "fan.h"
#include "gpio.h"
#include "host_command.h"
#include "i2c.h"
#include "jtag.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "peci.h"
#include "power.h"
#include "power_button.h"
#include "registers.h"
#include "switch.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "thermal.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_PP5000_PGOOD, 1, "PGOOD_PP5000"},
{GPIO_PP1350_PGOOD, 1, "PGOOD_PP1350"},
{GPIO_PP1050_PGOOD, 1, "PGOOD_PP1050"},
{GPIO_VCORE_PGOOD, 1, "PGOOD_VCORE"},
{GPIO_PCH_SLP_S0_L, 1, "SLP_S0#_DEASSERTED"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3#_DEASSERTED"},
{GPIO_PCH_SLP_S5_L, 1, "SLP_S5#_DEASSERTED"},
{GPIO_PCH_SLP_SUS_L, 1, "SLP_SUS#_DEASSERTED"},
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
const struct adc_t adc_channels[] = {
/* EC internal temperature is calculated by
* 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
* = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
*/
{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
/* IOUT == ICMNT is on PE3/AIN0 */
/* We have 0.01-ohm resistors, and IOUT is 20X the differential
* voltage, so 1000mA ==> 200mV.
* ADC returns 0x000-0xFFF, which maps to 0.0-3.3V (as configured).
* mA = 1000 * ADC_VALUE / ADC_READ_MAX * 3300 / 200
*/
{"ChargerCurrent", LM4_ADC_SEQ1, 33000, ADC_READ_MAX * 2, 0,
LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* Physical fans. These are logically separate from pwm_channels. */
const struct fan_t fans[] = {
{.flags = FAN_USE_RPM_MODE,
.rpm_min = 1000,
.rpm_start = 1000,
.rpm_max = 5050,
.ch = 2,
.pgood_gpio = GPIO_PP5000_PGOOD,
.enable_gpio = GPIO_PP5000_FAN_EN,
},
};
BUILD_ASSERT(ARRAY_SIZE(fans) == CONFIG_FANS);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"batt_chg", 0, 100},
{"thermal", 5, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/* Temperature sensors data; must be in same order as enum temp_sensor_id. */
const struct temp_sensor_t temp_sensors[] = {
{"PECI", TEMP_SENSOR_TYPE_CPU, peci_temp_sensor_get_val, 0, 2},
{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
{"G781Internal", TEMP_SENSOR_TYPE_BOARD, g78x_get_val,
G78X_IDX_INTERNAL, 4},
{"G781External", TEMP_SENSOR_TYPE_BOARD, g78x_get_val,
G78X_IDX_EXTERNAL1, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
/* Thermal limits for each temp sensor. All temps are in degrees K. Must be in
* same order as enum temp_sensor_id. To always ignore any temp, use 0.
*/
struct ec_thermal_config thermal_params[] = {
/* Only the AP affects the thermal limits and fan speed. */
{{C_TO_K(95), C_TO_K(97), C_TO_K(99)}, C_TO_K(55), C_TO_K(85)},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
{{0, 0, 0}, 0, 0},
};
BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
struct keyboard_scan_config keyscan_config = {
.output_settle_us = 40,
.debounce_down_us = 6 * MSEC,
.debounce_up_us = 30 * MSEC,
.scan_period_us = 1500,
.min_post_scan_delay_us = 1000,
.poll_timeout_us = SECOND,
.actual_key_mask = {
0x14, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
0xa4, 0xff, 0xf6, 0x55, 0xfa, 0xca /* full set */
},
};
/**
* Discharge battery when on AC power for factory test.
*/
int board_discharge_on_ac(int enable)
{
if (enable)
gpio_set_level(GPIO_CHARGE_L, 1);
else
gpio_set_level(GPIO_CHARGE_L, 0);
return EC_SUCCESS;
}

117
board/auron/board.h
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@@ -1,117 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Configuration for Auron mainboard */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_BACKLIGHT_LID
#define CONFIG_BACKLIGHT_REQ_GPIO GPIO_PCH_BKLTEN
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_PRESENT_GPIO GPIO_BAT_PRESENT_L
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V1
#define CONFIG_CHARGER_BQ24707A
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
#define CONFIG_CHIPSET_CAN_THROTTLE
#define CONFIG_CHIPSET_HASWELL
#define CONFIG_I2C
#define CONFIG_I2C_MASTER
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
#define CONFIG_CMD_GSV
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_FANS 1
#define CONFIG_KEYBOARD_BOARD_CONFIG
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_COMMON
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_PECI_TJMAX 100
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_SWITCH_DEDICATED_RECOVERY
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_G781
#define CONFIG_TEMP_SENSOR_POWER_GPIO GPIO_PP3300_DX_EN
#define CONFIG_THROTTLE_AP
#define CONFIG_UART_HOST 2
#define CONFIG_USB_PORT_POWER_DUMB
#define CONFIG_VBOOT_HASH
#define CONFIG_WIRELESS
#ifndef __ASSEMBLER__
/* I2C ports */
#define I2C_PORT_BATTERY 0
#define I2C_PORT_CHARGER 0
#define I2C_PORT_THERMAL 5
/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
#define KB_SCAN_ROW_IRQ LM4_IRQ_GPIOK
#define KB_SCAN_ROW_GPIO LM4_GPIO_K
/* Host connects to keyboard controller module via LPC */
#define HOST_KB_BUS_LPC
/* USB ports */
#define USB_PORT_COUNT 2
#include "gpio_signal.h"
/* power signal definitions */
enum power_signal {
X86_PGOOD_PP5000 = 0,
X86_PGOOD_PP1350,
X86_PGOOD_PP1050,
X86_PGOOD_VCORE,
X86_SLP_S0_DEASSERTED,
X86_SLP_S3_DEASSERTED,
X86_SLP_S5_DEASSERTED,
X86_SLP_SUS_DEASSERTED,
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
/* Charger module */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input sensor resistor, mOhm */
#define CONFIG_CHARGER_INPUT_CURRENT 3078 /* mA, 90% of power supply rating */
enum adc_channel {
/* EC internal die temperature in degrees K. */
ADC_CH_EC_TEMP = 0,
/* Charger current in mA. */
ADC_CH_CHARGER_CURRENT,
ADC_CH_COUNT
};
enum temp_sensor_id {
/* CPU die temperature via PECI */
TEMP_SENSOR_CPU_PECI = 0,
/* EC internal temperature sensor */
TEMP_SENSOR_EC_INTERNAL,
/* G781 internal and external sensors */
TEMP_SENSOR_I2C_G781_INTERNAL,
TEMP_SENSOR_I2C_G781_EXTERNAL,
TEMP_SENSOR_COUNT
};
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

12
board/auron/build.mk
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# -*- makefile -*-
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is TI Stellaris LM4
CHIP:=lm4
board-y=board.o battery.o led.o

27
board/auron/ec.tasklist
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@@ -1,27 +0,0 @@
/* Copyright 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' is the name of the task
* 'r' is the main routine of the task
* 'd' is an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

103
board/auron/gpio.inc
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/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(POWER_BUTTON_L, PIN(A, 2), GPIO_INT_BOTH_DSLEEP, power_button_interrupt) /* Power button */
GPIO_INT(LID_OPEN, PIN(A, 3), GPIO_INT_BOTH_DSLEEP, lid_interrupt) /* Lid switch */
GPIO_INT(AC_PRESENT, PIN(H, 3), GPIO_INT_BOTH_DSLEEP, extpower_interrupt) /* AC power present */
GPIO_INT(PCH_BKLTEN, PIN(M, 3), GPIO_INT_BOTH, backlight_interrupt) /* Backlight enable signal from PCH */
GPIO_INT(PCH_SLP_S0_L, PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_S0# signal from PCH */
GPIO_INT(PCH_SLP_S3_L, PIN(G, 7), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S3# signal from PCH */
GPIO_INT(PCH_SLP_S5_L, PIN(H, 1), GPIO_INT_BOTH_DSLEEP, power_signal_interrupt) /* SLP_S5# signal from PCH */
GPIO_INT(PCH_SLP_SUS_L, PIN(G, 3), GPIO_INT_BOTH, power_signal_interrupt) /* SLP_SUS# signal from PCH */
GPIO_INT(PP1050_PGOOD, PIN(H, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.05V */
GPIO_INT(PP1350_PGOOD, PIN(H, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.35V (DRAM) */
GPIO_INT(PP5000_PGOOD, PIN(N, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 5V */
GPIO_INT(VCORE_PGOOD, PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on core VR */
GPIO_INT(PCH_EDP_VDD_EN, PIN(J, 1), GPIO_INT_BOTH, power_interrupt) /* PCH wants EDP enabled */
GPIO_INT(RECOVERY_L, PIN(A, 5), GPIO_PULL_UP | GPIO_INT_BOTH, switch_interrupt) /* Recovery signal from servo */
GPIO_INT(WP_L, PIN(A, 4), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */
GPIO_INT(JTAG_TCK, PIN(C, 0), GPIO_DEFAULT, jtag_interrupt) /* JTAG clock input */
GPIO_INT(UART0_RX, PIN(A, 0), GPIO_PULL_UP | GPIO_INT_BOTH_DSLEEP, uart_deepsleep_interrupt) /* UART0 RX input */
/* Other inputs */
GPIO(FAN_ALERT_L, PIN(B, 0), GPIO_INPUT) /* From thermal sensor */
GPIO(PCH_SUSWARN_L, PIN(G, 2), GPIO_INT_BOTH) /* SUSWARN# signal from PCH */
GPIO(USB1_OC_L, PIN(E, 7), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(USB2_OC_L, PIN(E, 0), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(BOARD_VERSION1, PIN(Q, 5), GPIO_INPUT) /* Board version stuffing resistor 1 */
GPIO(BOARD_VERSION2, PIN(Q, 6), GPIO_INPUT) /* Board version stuffing resistor 2 */
GPIO(BOARD_VERSION3, PIN(Q, 7), GPIO_INPUT) /* Board version stuffing resistor 3 */
GPIO(CPU_PGOOD, PIN(C, 4), GPIO_INPUT) /* Power good to the CPU */
GPIO(BAT_PRESENT_L, PIN(B, 4), GPIO_INPUT) /* Battery present. Repurposed BAT_TEMP */
/* Outputs; all unasserted by default except for reset signals */
GPIO(CPU_PROCHOT, PIN(B, 1), GPIO_OUT_LOW) /* Force CPU to think it's overheated */
GPIO(PP1350_EN, PIN(H, 5), GPIO_OUT_LOW) /* Enable 1.35V supply */
GPIO(PP3300_DX_EN, PIN(J, 2), GPIO_OUT_LOW) /* Enable power to lots of peripherals */
GPIO(PP3300_LTE_EN, PIN(D, 2), GPIO_OUT_LOW) /* Enable LTE radio */
GPIO(PP3300_WLAN_EN, PIN(J, 0), GPIO_OUT_LOW) /* Enable WiFi power */
GPIO(SUSP_VR_EN, PIN(C, 7), GPIO_OUT_LOW) /* Enable 1.05V regulator */
GPIO(VCORE_EN, PIN(C, 5), GPIO_OUT_LOW) /* Stuffing option - not connected */
GPIO(PP5000_EN, PIN(H, 7), GPIO_OUT_LOW) /* Enable 5V supply */
GPIO(PP5000_FAN_EN, PIN(J, 3), GPIO_OUT_LOW) /* Enable fan power rail */
GPIO(SYS_PWROK, PIN(H, 2), GPIO_OUT_LOW) /* EC thinks everything is up and ready */
GPIO(WLAN_OFF_L, PIN(J, 4), GPIO_OUT_LOW) /* Disable WiFi radio */
GPIO(CHARGE_L, PIN(E, 6), GPIO_OUT_LOW) /* Allow battery to charge when on AC */
GPIO(ENABLE_BACKLIGHT, PIN(M, 7), GPIO_OUT_LOW) /* Enable backlight power */
GPIO(ENABLE_TOUCHPAD, PIN(N, 1), GPIO_OUT_LOW) /* Enable touchpad power */
GPIO(ENTERING_RW, PIN(D, 3), GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(PCH_DPWROK, PIN(G, 0), GPIO_OUT_LOW) /* Indicate when VccDSW is good */
/*
* HDA_SDO is technically an output, but we need to leave it as an
* input until we drive it high. So can't use open-drain (HI_Z).
*/
GPIO(PCH_HDA_SDO, PIN(G, 1), GPIO_INPUT) /* HDA_SDO signal to PCH; when high, ME ignores security descriptor */
GPIO(PCH_WAKE_L, PIN(F, 0), GPIO_OUT_HIGH) /* Wake signal from EC to PCH */
GPIO(PCH_NMI_L, PIN(F, 2), GPIO_OUT_HIGH) /* Non-maskable interrupt pin to PCH */
GPIO(PCH_PWRBTN_L, PIN(H, 0), GPIO_OUT_HIGH) /* Power button output to PCH */
GPIO(PCH_PWROK, PIN(F, 5), GPIO_OUT_LOW) /* PWROK / APWROK signals to PCH */
/*
* PL6 is one of 4 pins on the EC which can't be used in open-drain
* mode. To work around this PCH_RCIN_L is set to an input. It will
* only be set to an output when it needs to be driven to 0.
*/
GPIO(PCH_RCIN_L, PIN(L, 6), GPIO_INPUT) /* RCIN# line to PCH (for 8042 emulation) */
GPIO(PCH_RSMRST_L, PIN(F, 1), GPIO_OUT_LOW) /* Reset PCH resume power plane logic */
GPIO(PCH_SMI_L, PIN(F, 4), GPIO_ODR_HIGH) /* System management interrupt to PCH */
GPIO(TOUCHSCREEN_RESET_L, PIN(N, 7), GPIO_OUT_LOW) /* Reset touch screen */
GPIO(EC_EDP_VDD_EN, PIN(J, 5), GPIO_OUT_LOW) /* Enable EDP (passthru from PCH) */
GPIO(LPC_CLKRUN_L, PIN(M, 2), GPIO_ODR_HIGH) /* Dunno. Probably important, though. */
GPIO(USB1_ENABLE, PIN(E, 4), GPIO_OUT_LOW) /* USB port 1 output power enable */
GPIO(USB2_ENABLE, PIN(D, 5), GPIO_OUT_LOW) /* USB port 2 output power enable */
GPIO(PCH_SUSACK_L, PIN(F, 3), GPIO_OUT_HIGH) /* Acknowledge PCH SUSWARN# signal */
GPIO(PCH_RTCRST_L, PIN(F, 6), GPIO_ODR_HIGH) /* Not supposed to be here */
GPIO(PCH_SRTCRST_L, PIN(F, 7), GPIO_ODR_HIGH) /* Not supposed to be here */
GPIO(BAT_LED0_L, PIN(D, 0), GPIO_ODR_HIGH) /* Battery charging LED - blue */
GPIO(BAT_LED1_L, PIN(N, 4), GPIO_ODR_HIGH) /* Battery charging LED - orange */
GPIO(PWR_LED0_L, PIN(D, 1), GPIO_ODR_HIGH) /* Power LED - blue */
GPIO(PWR_LED1_L, PIN(N, 6), GPIO_ODR_HIGH) /* Power LED - orange */
ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART, GPIO_PULL_UP) /* UART0 */
ALTERNATE(PIN_MASK(B, 0x04), 3, MODULE_I2C, 0) /* I2C0 SCL */
ALTERNATE(PIN_MASK(B, 0x08), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C0 SDA */
ALTERNATE(PIN_MASK(B, 0x40), 3, MODULE_I2C, 0) /* I2C5 SCL */
ALTERNATE(PIN_MASK(B, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C5 SDA */
ALTERNATE(PIN_MASK(G, 0x30), 1, MODULE_UART, 0) /* UART2 */
ALTERNATE(PIN_MASK(J, 0x40), 1, MODULE_PECI, 0) /* PECI Tx */
ALTERNATE(PIN_MASK(J, 0x80), 0, MODULE_PECI, GPIO_ANALOG) /* PECI Rx */
ALTERNATE(PIN_MASK(L, 0x3f), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(M, 0x33), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(N, 0x0c), 1, MODULE_PWM, 0) /* FAN0PWM2 */

186
board/auron/led.c
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@@ -1,186 +0,0 @@
/* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Power and battery LED control for Auron.
*/
#include "battery.h"
#include "charge_state.h"
#include "chipset.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "host_command.h"
#include "led_common.h"
#include "util.h"
#define LED_TOTAL_TICKS 16
#define LED_ON_TICKS 4
enum led_color {
LED_OFF = 0,
LED_BLUE,
LED_AMBER,
LED_PINK,
LED_COLOR_COUNT /* Number of colors, not a color itself */
};
const enum ec_led_id supported_led_ids[] = {
EC_LED_ID_POWER_LED, EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
static int auron_led_set_gpio(enum led_color color,
enum gpio_signal gpio_led_blue_l,
enum gpio_signal gpio_led_amber_l)
{
switch (color) {
case LED_OFF:
gpio_set_level(gpio_led_blue_l, 1);
gpio_set_level(gpio_led_amber_l, 1);
break;
case LED_BLUE:
gpio_set_level(gpio_led_blue_l, 0);
gpio_set_level(gpio_led_amber_l, 1);
break;
case LED_AMBER:
gpio_set_level(gpio_led_blue_l, 1);
gpio_set_level(gpio_led_amber_l, 0);
break;
case LED_PINK:
gpio_set_level(gpio_led_blue_l, 0);
gpio_set_level(gpio_led_amber_l, 0);
break;
default:
return EC_ERROR_UNKNOWN;
}
return EC_SUCCESS;
}
static int auron_led_set_color_battery(enum led_color color)
{
return auron_led_set_gpio(color, GPIO_BAT_LED0_L, GPIO_BAT_LED1_L);
}
static int auron_led_set_color_power(enum led_color color)
{
return auron_led_set_gpio(color, GPIO_PWR_LED0_L, GPIO_PWR_LED1_L);
}
static int auron_led_set_color(enum ec_led_id led_id, enum led_color color)
{
int rv;
led_auto_control(led_id, 0);
switch (led_id) {
case EC_LED_ID_BATTERY_LED:
rv = auron_led_set_color_battery(color);
break;
case EC_LED_ID_POWER_LED:
rv = auron_led_set_color_power(color);
break;
default:
return EC_ERROR_UNKNOWN;
}
return rv;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
if (brightness[EC_LED_COLOR_BLUE] != 0 &&
brightness[EC_LED_COLOR_YELLOW] != 0)
auron_led_set_color(led_id, LED_PINK);
else if (brightness[EC_LED_COLOR_BLUE] != 0)
auron_led_set_color(led_id, LED_BLUE);
else if (brightness[EC_LED_COLOR_YELLOW] != 0)
auron_led_set_color(led_id, LED_AMBER);
else
auron_led_set_color(led_id, LED_OFF);
return EC_SUCCESS;
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
/* Ignoring led_id as both leds support the same colors */
brightness_range[EC_LED_COLOR_BLUE] = 1;
brightness_range[EC_LED_COLOR_YELLOW] = 1;
}
static void auron_led_set_power(void)
{
static int power_ticks;
static int previous_state_suspend;
power_ticks++;
if (chipset_in_state(CHIPSET_STATE_SUSPEND)) {
/* Reset ticks if entering suspend so LED turns amber
* as soon as possible. */
if (!previous_state_suspend)
power_ticks = 0;
/* Blink once every four seconds. */
auron_led_set_color_power(
(power_ticks % LED_TOTAL_TICKS < LED_ON_TICKS) ?
LED_AMBER : LED_OFF);
previous_state_suspend = 1;
return;
}
previous_state_suspend = 0;
if (chipset_in_state(CHIPSET_STATE_ANY_OFF))
auron_led_set_color_power(LED_OFF);
else if (chipset_in_state(CHIPSET_STATE_ON))
auron_led_set_color_power(LED_BLUE);
}
static void auron_led_set_battery(void)
{
static int battery_ticks;
uint32_t chflags = charge_get_flags();
battery_ticks++;
switch (charge_get_state()) {
case PWR_STATE_CHARGE:
auron_led_set_color_battery(LED_AMBER);
break;
case PWR_STATE_CHARGE_NEAR_FULL:
auron_led_set_color_battery(LED_BLUE);
break;
case PWR_STATE_DISCHARGE:
auron_led_set_color_battery(LED_OFF);
break;
case PWR_STATE_ERROR:
auron_led_set_color_battery(
(battery_ticks % LED_TOTAL_TICKS < LED_ON_TICKS) ?
LED_AMBER : LED_OFF);
break;
case PWR_STATE_IDLE: /* External power connected in IDLE. */
if (chflags & CHARGE_FLAG_FORCE_IDLE)
auron_led_set_color_battery(
(battery_ticks & 0x4) ? LED_BLUE : LED_OFF);
else
auron_led_set_color_battery(LED_BLUE);
break;
default:
/* Other states don't alter LED behavior */
break;
}
}
/* Called by hook task every 250mSec */
static void led_tick(void)
{
if (led_auto_control_is_enabled(EC_LED_ID_POWER_LED))
auron_led_set_power();
if (led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
auron_led_set_battery();
}
DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);

47
board/rambi/battery.c
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@@ -1,47 +0,0 @@
/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery pack vendor provided charging profile
*/
#include "battery.h"
#include "battery_smart.h"
#include "console.h"
#include "gpio.h"
#include "host_command.h"
#include "util.h"
/* Shutdown mode parameter to write to manufacturer access register */
#define SB_SHUTDOWN_DATA 0x0010
static const struct battery_info info = {
.voltage_max = 8400, /* mV */
.voltage_normal = 7400,
.voltage_min = 6000,
.precharge_current = 256, /* mA */
.start_charging_min_c = 0,
.start_charging_max_c = 45,
.charging_min_c = 0,
.charging_max_c = 45,
.discharging_min_c = 0,
.discharging_max_c = 60,
};
const struct battery_info *battery_get_info(void)
{
return &info;
}
int board_cut_off_battery(void)
{
int rv;
/* Ship mode command must be sent twice to take effect */
rv = sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
if (rv != EC_SUCCESS)
return rv;
return sb_write(SB_MANUFACTURER_ACCESS, SB_SHUTDOWN_DATA);
}

110
board/rambi/board.c
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@@ -1,110 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* EC for Rambi board configuration */
#include "adc.h"
#include "adc_chip.h"
#include "backlight.h"
#include "charge_state.h"
#include "charger.h"
#include "common.h"
#include "driver/temp_sensor/tmp432.h"
#include "extpower.h"
#include "gpio.h"
#include "host_command.h"
#include "i2c.h"
#include "jtag.h"
#include "keyboard_scan.h"
#include "lid_switch.h"
#include "peci.h"
#include "power.h"
#include "power_button.h"
#include "pwm.h"
#include "pwm_chip.h"
#include "registers.h"
#include "switch.h"
#include "temp_sensor.h"
#include "temp_sensor_chip.h"
#include "thermal.h"
#include "timer.h"
#include "uart.h"
#include "util.h"
#include "gpio_list.h"
/* power signal list. Must match order of enum power_signal. */
const struct power_signal_info power_signal_list[] = {
{GPIO_PP1050_PGOOD, 1, "PGOOD_PP1050"},
{GPIO_PP3300_PCH_PGOOD, 1, "PGOOD_PP3300_PCH"},
{GPIO_PP5000_PGOOD, 1, "PGOOD_PP5000"},
{GPIO_S5_PGOOD, 1, "PGOOD_S5"},
{GPIO_VCORE_PGOOD, 1, "PGOOD_VCORE"},
{GPIO_PP1000_S0IX_PGOOD, 1, "PGOOD_PP1000_S0IX"},
{GPIO_PCH_SLP_S3_L, 1, "SLP_S3#_DEASSERTED"},
{GPIO_PCH_SLP_S4_L, 1, "SLP_S4#_DEASSERTED"},
#ifdef CONFIG_CHIPSET_DEBUG
{GPIO_PCH_SLP_SX_L, 1, "SLP_SX#_DEASSERTED"},
{GPIO_PCH_SUS_STAT_L, 0, "SUS_STAT#_ASSERTED"},
{GPIO_PCH_SUSPWRDNACK, 1, "SUSPWRDNACK_ASSERTED"},
#endif
};
BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
/* ADC channels. Must be in the exactly same order as in enum adc_channel. */
const struct adc_t adc_channels[] = {
/* EC internal temperature is calculated by
* 273 + (295 - 450 * ADC_VALUE / ADC_READ_MAX) / 2
* = -225 * ADC_VALUE / ADC_READ_MAX + 420.5
*/
{"ECTemp", LM4_ADC_SEQ0, -225, ADC_READ_MAX, 420,
LM4_AIN_NONE, 0x0e /* TS0 | IE0 | END0 */, 0, 0},
/* IOUT == ICMNT is on PE3/AIN0 */
/* We have 0.01-ohm resistors, and IOUT is 40X the differential
* voltage, so 1000mA ==> 400mV.
* ADC returns 0x000-0xFFF, which maps to 0.0-3.3V (as configured).
* mA = 1000 * ADC_VALUE / ADC_READ_MAX * 3300 / 400
*/
{"ChargerCurrent", LM4_ADC_SEQ1, 33000, ADC_READ_MAX * 4, 0,
LM4_AIN(0), 0x06 /* IE0 | END0 */, LM4_GPIO_E, (1<<3)},
};
BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
{4, PWM_CONFIG_ACTIVE_LOW},
{3, PWM_CONFIG_ACTIVE_LOW},
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
/* I2C ports */
const struct i2c_port_t i2c_ports[] = {
{"batt_chg", 0, 100},
{"thermal", 5, 100},
};
const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
/*
* Temperature sensors data; must be in same order as enum temp_sensor_id.
* Sensor index and name must match those present in coreboot:
* src/mainboard/google/${board}/acpi/dptf.asl
*/
const struct temp_sensor_t temp_sensors[] = {
{"ECInternal", TEMP_SENSOR_TYPE_BOARD, chip_temp_sensor_get_val, 0, 4},
{"TMP432_Internal", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_LOCAL, 4},
{"TMP432_Power_top", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_REMOTE1, 4},
{"TMP432_CPU_bottom", TEMP_SENSOR_TYPE_BOARD, tmp432_get_val,
TMP432_IDX_REMOTE2, 4},
{"Battery", TEMP_SENSOR_TYPE_BATTERY, charge_get_battery_temp, 0, 4},
};
BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
int board_allow_i2c_passthru(int port)
{
return 0;
}

133
board/rambi/board.h
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@@ -1,133 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Configuration for Rambi mainboard */
#ifndef __CROS_EC_BOARD_H
#define __CROS_EC_BOARD_H
/* Optional features */
#define CONFIG_AP_HANG_DETECT
#define CONFIG_BACKLIGHT_LID
#define CONFIG_BATTERY_CUT_OFF
#define CONFIG_BATTERY_SMART
#define CONFIG_BOARD_VERSION
#define CONFIG_CHARGER
#define CONFIG_CHARGER_V1
#define CONFIG_CHARGER_BQ24715
#define CONFIG_CHARGER_DISCHARGE_ON_AC
#define CONFIG_CHARGER_INPUT_CURRENT 1700 /* 33 W adapter, 19 V, 1.75 A */
#define CONFIG_CHARGER_SENSE_RESISTOR 10 /* Charge sense resistor, mOhm */
#define CONFIG_CHARGER_SENSE_RESISTOR_AC 10 /* Input senso resistor, mOhm */
#define CONFIG_CHIPSET_BAYTRAIL
#define CONFIG_CHIPSET_CAN_THROTTLE
#define CONFIG_POWER_COMMON
#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
#define CONFIG_CMD_GSV
#define CONFIG_EXTPOWER_GPIO
#define CONFIG_I2C
#define CONFIG_I2C_MASTER
#define CONFIG_I2C_PASSTHRU_RESTRICTED
#define CONFIG_KEYBOARD_COL2_INVERTED
#define CONFIG_KEYBOARD_IRQ_GPIO GPIO_KBD_IRQ_L
#define CONFIG_KEYBOARD_PROTOCOL_8042
#define CONFIG_LED_COMMON
#define CONFIG_LOW_POWER_IDLE
#undef CONFIG_PECI
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_PWM
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
#define CONFIG_TEMP_SENSOR
#define CONFIG_TEMP_SENSOR_TMP432
#define CONFIG_DPTF
#define CONFIG_USB_PORT_POWER_IN_S3
#define CONFIG_USB_PORT_POWER_SMART
#define CONFIG_USB_PORT_POWER_SMART_SIMPLE
#define CONFIG_VBOOT_HASH
#define CONFIG_WIRELESS
#define CONFIG_WIRELESS_SUSPEND \
(EC_WIRELESS_SWITCH_WLAN | EC_WIRELESS_SWITCH_WLAN_POWER)
#ifndef __ASSEMBLER__
/* I2C ports */
#define I2C_PORT_BATTERY 0
#define I2C_PORT_CHARGER 0
#define I2C_PORT_THERMAL 5
/* 13x8 keyboard scanner uses an entire GPIO bank for row inputs */
#define KB_SCAN_ROW_IRQ LM4_IRQ_GPIOK
#define KB_SCAN_ROW_GPIO LM4_GPIO_K
/* Host connects to keyboard controller module via LPC */
#define HOST_KB_BUS_LPC
/* USB ports */
#define USB_PORT_COUNT 2
/* Wireless signals */
#define WIRELESS_GPIO_WLAN GPIO_WLAN_OFF_L
#define WIRELESS_GPIO_WWAN GPIO_PP3300_LTE_EN
#define WIRELESS_GPIO_WLAN_POWER GPIO_PP3300_WLAN_EN
#include "gpio_signal.h"
/* power signal definitions */
enum power_signal {
X86_PGOOD_PP1050 = 0,
X86_PGOOD_PP3300_PCH,
X86_PGOOD_PP5000,
X86_PGOOD_S5,
X86_PGOOD_VCORE,
X86_PGOOD_PP1000_S0IX,
X86_SLP_S3_DEASSERTED,
X86_SLP_S4_DEASSERTED,
#ifdef CONFIG_CHIPSET_DEBUG
X86_SLP_SX_DEASSERTED,
X86_SUS_STAT_ASSERTED,
X86_SUSPWRDNACK_ASSERTED,
#endif
/* Number of X86 signals */
POWER_SIGNAL_COUNT
};
enum adc_channel {
/* EC internal die temperature in degrees K. */
ADC_CH_EC_TEMP = 0,
/* Charger current in mA. */
ADC_CH_CHARGER_CURRENT,
ADC_CH_COUNT
};
enum pwm_channel {
PWM_CH_LED_GREEN,
PWM_CH_LED_RED,
/* Number of PWM channels */
PWM_CH_COUNT
};
enum temp_sensor_id {
/* EC internal temperature sensor */
TEMP_SENSOR_EC_INTERNAL = 0,
/* TMP432 local and remote sensors */
TEMP_SENSOR_I2C_TMP432_LOCAL,
TEMP_SENSOR_I2C_TMP432_REMOTE1,
TEMP_SENSOR_I2C_TMP432_REMOTE2,
/* Battery temperature sensor */
TEMP_SENSOR_BATTERY,
TEMP_SENSOR_COUNT
};
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BOARD_H */

12
board/rambi/build.mk
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@@ -1,12 +0,0 @@
# -*- makefile -*-
# Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
# Use of this source code is governed by a BSD-style license that can be
# found in the LICENSE file.
#
# Board specific files build
#
# the IC is TI Stellaris LM4
CHIP:=lm4
board-y=battery.o board.o led.o

28
board/rambi/ec.tasklist
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@@ -1,28 +0,0 @@
/* -*- c -*- */
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/**
* List of enabled tasks in the priority order
*
* The first one has the lowest priority.
*
* For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
* TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
* where :
* 'n' is the name of the task
* 'r' is the main routine of the task
* 'd' is an opaque parameter passed to the routine at startup
* 's' is the stack size in bytes; must be a multiple of 8
*/
#define CONFIG_TASK_LIST \
TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(CHARGER, charger_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(CHIPSET, chipset_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE) \
TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)

79
board/rambi/gpio.inc
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@@ -1,79 +0,0 @@
/* -*- mode:c -*-
*
* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* Declare symbolic names for all the GPIOs that we care about.
* Note: Those with interrupt handlers must be declared first. */
GPIO_INT(POWER_BUTTON_L, PIN(A, 2), GPIO_INT_BOTH_DSLEEP, power_button_interrupt)
GPIO_INT(LID_OPEN, PIN(A, 3), GPIO_INT_BOTH_DSLEEP, lid_interrupt)
GPIO_INT(AC_PRESENT, PIN(H, 3), GPIO_INT_BOTH_DSLEEP, extpower_interrupt)
GPIO_INT(PCH_SLP_S3_L, PIN(G, 7), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, power_signal_interrupt) /* SLP_S3# signal from PCH */
GPIO_INT(PCH_SLP_S4_L, PIN(H, 1), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, power_signal_interrupt) /* SLP_S4# signal from PCH */
GPIO_INT(PP1050_PGOOD, PIN(H, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 1.05V */
GPIO_INT(PP3300_PCH_PGOOD, PIN(C, 4), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 3.3V (PCH supply) */
GPIO_INT(PP5000_PGOOD, PIN(N, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on 5V */
GPIO_INT(S5_PGOOD, PIN(G, 0), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on S5 supplies */
GPIO_INT(VCORE_PGOOD, PIN(C, 6), GPIO_INT_BOTH, power_signal_interrupt) /* Power good on core VR */
GPIO_INT(WP_L, PIN(A, 4), GPIO_INT_BOTH, switch_interrupt) /* Write protect input */
GPIO_INT(JTAG_TCK, PIN(C, 0), GPIO_DEFAULT, jtag_interrupt) /* JTAG clock input */
GPIO_INT(UART0_RX, PIN(A, 0), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt) /* UART0 RX input */
/* Other inputs */
GPIO(BOARD_VERSION1, PIN(Q, 5), GPIO_INPUT)
GPIO(BOARD_VERSION2, PIN(Q, 6), GPIO_INPUT)
GPIO(BOARD_VERSION3, PIN(Q, 7), GPIO_INPUT)
#ifdef CONFIG_CHIPSET_DEBUG
GPIO(PCH_SLP_SX_L, PIN(G, 3), GPIO_INPUT | GPIO_PULL_UP) /* SLP_S0IX# signal from PCH */
GPIO(PCH_SUS_STAT_L, PIN(G, 6), GPIO_INPUT | GPIO_PULL_UP) /* SUS_STAT# signal from PCH */
GPIO(PCH_SUSPWRDNACK, PIN(G, 2), GPIO_INPUT | GPIO_PULL_UP) /* SUSPWRDNACK signal from PCH */
#endif
GPIO(PP1000_S0IX_PGOOD, PIN(H, 6), GPIO_INPUT) /* Power good on 1.00V (S0iX supplies) */
GPIO(USB1_OC_L, PIN(E, 7), GPIO_INPUT) /* USB port overcurrent warning */
GPIO(USB2_OC_L, PIN(E, 0), GPIO_INPUT) /* USB port overcurrent warning */
/* Outputs; all unasserted by default except for reset signals */
GPIO(CPU_PROCHOT, PIN(B, 5), GPIO_OUT_LOW) /* Force CPU to think it's overheated */
GPIO(ENABLE_BACKLIGHT, PIN(M, 7), GPIO_ODR_HIGH) /* Enable backlight power */
GPIO(ENABLE_TOUCHPAD, PIN(N, 1), GPIO_OUT_LOW) /* Enable touchpad power */
GPIO(ENTERING_RW, PIN(D, 6), GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(LPC_CLKRUN_L, PIN(M, 2), GPIO_ODR_HIGH) /* Request that PCH drive LPC clock */
GPIO(PCH_CORE_PWROK, PIN(F, 5), GPIO_OUT_LOW) /* Indicate core well power is stable */
GPIO(PCH_PWRBTN_L, PIN(H, 0), GPIO_ODR_HIGH) /* Power button output to PCH */
GPIO(PCH_RCIN_L, PIN(F, 3), GPIO_ODR_HIGH) /* Reset line to PCH (for 8042 emulation) */
GPIO(PCH_RSMRST_L, PIN(F, 1), GPIO_OUT_LOW) /* Reset PCH resume power plane logic */
GPIO(PCH_SMI_L, PIN(F, 4), GPIO_ODR_HIGH) /* System management interrupt to PCH */
GPIO(PCH_SOC_OVERRIDE, PIN(G, 1), GPIO_OUT_LOW) /* SOC override signal to PCH; when high, ME ignores security descriptor */
GPIO(PCH_SYS_PWROK, PIN(J, 1), GPIO_OUT_LOW) /* EC thinks everything is up and ready */
GPIO(PCH_WAKE_L, PIN(F, 0), GPIO_ODR_HIGH) /* Wake signal from EC to PCH */
GPIO(PP1350_EN, PIN(H, 5), GPIO_OUT_LOW) /* Enable 1.35V supply */
GPIO(PP3300_DX_EN, PIN(J, 2), GPIO_OUT_LOW) /* Enable power to lots of peripherals */
GPIO(PP3300_LTE_EN, PIN(D, 4), GPIO_OUT_LOW) /* Enable LTE radio */
GPIO(PP3300_WLAN_EN, PIN(J, 0), GPIO_OUT_LOW) /* Enable WiFi power */
GPIO(PP5000_EN, PIN(H, 7), GPIO_OUT_LOW) /* Enable 5V supply */
GPIO(PPSX_EN, PIN(L, 6), GPIO_OUT_LOW) /* Enable PP1350_PCH_SX, PP1000_PCH_SX */
GPIO(SUSP_VR_EN, PIN(C, 7), GPIO_OUT_LOW) /* Enable 1.05V regulator */
GPIO(TOUCHSCREEN_RESET_L, PIN(N, 7), GPIO_OUT_LOW) /* Reset touch screen */
GPIO(USB_CTL1, PIN(E, 6), GPIO_OUT_LOW) /* USB control signal 1 to both ports */
GPIO(USB_ILIM_SEL, PIN(E, 5), GPIO_OUT_LOW) /* USB current limit to both ports */
GPIO(USB1_ENABLE, PIN(E, 4), GPIO_OUT_LOW) /* USB port 1 output power enable */
GPIO(USB2_ENABLE, PIN(D, 5), GPIO_OUT_LOW) /* USB port 2 output power enable */
GPIO(VCORE_EN, PIN(C, 5), GPIO_OUT_LOW) /* Enable core power supplies */
GPIO(WLAN_OFF_L, PIN(J, 4), GPIO_OUT_LOW) /* Disable WiFi radio */
GPIO(PCH_SCI_L, PIN(M, 1), GPIO_ODR_HIGH) /* Assert SCI to PCH */
GPIO(KBD_IRQ_L, PIN(M, 3), GPIO_ODR_HIGH) /* Negative edge triggered irq. */
ALTERNATE(PIN_MASK(A, 0x03), 1, MODULE_UART, 0) /* UART0 */
ALTERNATE(PIN_MASK(B, 0x04), 3, MODULE_I2C, 0) /* I2C0 SCL */
ALTERNATE(PIN_MASK(B, 0x08), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C0 SDA */
ALTERNATE(PIN_MASK(B, 0x40), 3, MODULE_I2C, 0) /* I2C5 SCL */
ALTERNATE(PIN_MASK(B, 0x80), 3, MODULE_I2C, GPIO_OPEN_DRAIN) /* I2C5 SDA */
ALTERNATE(PIN_MASK(D, 0x0f), 2, MODULE_SPI, 0) /* SPI1 */
ALTERNATE(PIN_MASK(L, 0x3f), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(M, 0x21), 15, MODULE_LPC, 0) /* LPC */
ALTERNATE(PIN_MASK(N, 0x50), 1, MODULE_PWM, GPIO_OPEN_DRAIN) /* FAN0PWM 3&4 */

118
board/rambi/led.c
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@@ -1,118 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*
* Battery LED control for Rambi
*/
#include "charge_state.h"
#include "chipset.h"
#include "gpio.h"
#include "hooks.h"
#include "led_common.h"
#include "pwm.h"
#include "util.h"
const enum ec_led_id supported_led_ids[] = {EC_LED_ID_BATTERY_LED};
const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
enum led_color {
LED_OFF = 0,
LED_RED,
LED_ORANGE,
LED_YELLOW,
LED_GREEN,
/* Number of colors, not a color itself */
LED_COLOR_COUNT
};
/* Brightness vs. color, for {red, green} LEDs */
static const uint8_t color_brightness[LED_COLOR_COUNT][2] = {
{0, 0},
{100, 0},
{30, 45},
{20, 60},
{0, 100},
};
/**
* Set LED color
*
* @param color Enumerated color value
*/
static void set_color(enum led_color color)
{
pwm_set_duty(PWM_CH_LED_RED, color_brightness[color][0]);
pwm_set_duty(PWM_CH_LED_GREEN, color_brightness[color][1]);
}
void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
{
brightness_range[EC_LED_COLOR_RED] = 100;
brightness_range[EC_LED_COLOR_GREEN] = 100;
}
int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
{
pwm_set_duty(PWM_CH_LED_RED, brightness[EC_LED_COLOR_RED]);
pwm_set_duty(PWM_CH_LED_GREEN, brightness[EC_LED_COLOR_GREEN]);
return EC_SUCCESS;
}
static void led_init(void)
{
/*
* Enable PWMs and set to 0% duty cycle. If they're disabled, the LM4
* seems to ground the pins instead of letting them float.
*/
pwm_enable(PWM_CH_LED_RED, 1);
pwm_enable(PWM_CH_LED_GREEN, 1);
set_color(LED_OFF);
}
DECLARE_HOOK(HOOK_INIT, led_init, HOOK_PRIO_DEFAULT);
/**
* Called by hook task every 250 ms
*/
static void led_tick(void)
{
static unsigned ticks;
int chstate = charge_get_state();
ticks++;
/* If we don't control the LED, nothing to do */
if (!led_auto_control_is_enabled(EC_LED_ID_BATTERY_LED))
return;
/* If charging error, blink orange, 25% duty cycle, 4 sec period */
if (chstate == PWR_STATE_ERROR) {
set_color((ticks % 16) < 4 ? LED_ORANGE : LED_OFF);
return;
}
/* If charge-force-idle, blink green, 50% duty cycle, 2 sec period */
if (chstate == PWR_STATE_IDLE &&
(charge_get_flags() & CHARGE_FLAG_FORCE_IDLE)) {
set_color((ticks & 0x4) ? LED_GREEN : LED_OFF);
return;
}
/* If the system is charging, solid orange */
if (chstate == PWR_STATE_CHARGE) {
set_color(LED_ORANGE);
return;
}
/* If AC connected and fully charged (or close to it), solid green */
if (chstate == PWR_STATE_CHARGE_NEAR_FULL ||
chstate == PWR_STATE_IDLE) {
set_color(LED_GREEN);
return;
}
/* Otherwise, system is off and AC not connected, LED off */
set_color(LED_OFF);
}
DECLARE_HOOK(HOOK_TICK, led_tick, HOOK_PRIO_DEFAULT);

4
include/config.h
View File

@@ -564,11 +564,9 @@
/* AP chipset support; pick at most one */
#undef CONFIG_CHIPSET_APOLLOLAKE/* Intel Apollolake (x86) */
#undef CONFIG_CHIPSET_BAYTRAIL /* Intel Bay Trail (x86) */
#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */
#undef CONFIG_CHIPSET_ECDRIVEN /* Dummy power module */
#undef CONFIG_CHIPSET_GAIA /* Gaia and Ares (ARM) */
#undef CONFIG_CHIPSET_HASWELL /* Intel Haswell (x86) */
#undef CONFIG_CHIPSET_MEDIATEK /* MediaTek MT81xx */
#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */
/* TODO: Rename below config to CONFIG_CHIPSET_RK32XX */
@@ -2569,10 +2567,8 @@
#ifndef HAS_TASK_CHIPSET
#undef CONFIG_CHIPSET_APOLLOLAKE
#undef CONFIG_CHIPSET_BAYTRAIL
#undef CONFIG_CHIPSET_BRASWELL
#undef CONFIG_CHIPSET_GAIA
#undef CONFIG_CHIPSET_HASWELL
#undef CONFIG_CHIPSET_MEDIATEK
#undef CONFIG_CHIPSET_RK3399
#undef CONFIG_CHIPSET_ROCKCHIP

425
power/baytrail.c
View File

@@ -1,425 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* X86 baytrail chipset power control module for Chrome EC */
#include "chipset.h"
#include "common.h"
#include "console.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "lid_switch.h"
#include "lpc.h"
#include "power.h"
#include "power_button.h"
#include "system.h"
#include "timer.h"
#include "usb_charge.h"
#include "util.h"
#include "wireless.h"
/* Console output macros */
#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
/* Input state flags */
#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
#define IN_PGOOD_PP1050 POWER_SIGNAL_MASK(X86_PGOOD_PP1050)
#define IN_PGOOD_S5 POWER_SIGNAL_MASK(X86_PGOOD_S5)
#define IN_PGOOD_VCORE POWER_SIGNAL_MASK(X86_PGOOD_VCORE)
#define IN_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
#define IN_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
/* All always-on supplies */
#define IN_PGOOD_ALWAYS_ON (IN_PGOOD_S5)
/* All non-core power rails */
#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP5000)
/* All core power rails */
#define IN_PGOOD_ALL_CORE (IN_PGOOD_VCORE)
/* Rails required for S3 */
#define IN_PGOOD_S3 (IN_PGOOD_ALWAYS_ON)
/* Rails required for S0 */
#define IN_PGOOD_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
/* All PM_SLP signals from PCH deasserted */
#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | IN_SLP_S4_DEASSERTED)
/* All inputs in the right state for S0 */
#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE | \
IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
static int throttle_cpu; /* Throttle CPU? */
static int restart_from_s5; /* Force system back on from S5 */
static int fake_pltrst_timeout; /* Fake PLTRST# timeout at next power-on */
void chipset_force_shutdown(void)
{
CPRINTS("%s()", __func__);
/*
* Force power off. This condition will reset once the state machine
* transitions to G3.
*/
gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
}
void chipset_reset(int cold_reset)
{
CPRINTS("%s(%d)", __func__, cold_reset);
if (cold_reset) {
/*
* Drop and restore PWROK. This causes the PCH to reboot,
* regardless of its after-G3 setting. This type of reboot
* causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
* we actually drop power to the rest of the system (hence, a
* "cold" reboot).
*/
/* Ignore if PWROK is already low */
if (gpio_get_level(GPIO_PCH_SYS_PWROK) == 0)
return;
/* PWROK must deassert for at least 3 RTC clocks = 91 us */
gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
udelay(100);
gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
} else {
/*
* Send a reset pulse to the PCH. This just causes it to
* assert INIT# to the CPU without dropping power or asserting
* PLTRST# to reset the rest of the system. The PCH uses a 16
* ms debounce time, so assert the signal for twice that.
*/
gpio_set_level(GPIO_PCH_RCIN_L, 0);
usleep(32 * MSEC);
gpio_set_level(GPIO_PCH_RCIN_L, 1);
}
}
void chipset_throttle_cpu(int throttle)
{
if (chipset_in_state(CHIPSET_STATE_ON))
gpio_set_level(GPIO_CPU_PROCHOT, throttle);
}
enum power_state power_chipset_init(void)
{
/* Pause in S5 when shutting down. */
power_set_pause_in_s5(1);
/*
* If we're switching between images without rebooting, see if the x86
* is already powered on; if so, leave it there instead of cycling
* through G3.
*/
if (system_jumped_to_this_image()) {
if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
/* Disable idle task deep sleep when in S0. */
disable_sleep(SLEEP_MASK_AP_RUN);
CPRINTS("already in S0");
return POWER_S0;
} else {
/* Force all signals to their G3 states */
CPRINTS("forcing G3");
gpio_set_level(GPIO_PCH_CORE_PWROK, 0);
gpio_set_level(GPIO_VCORE_EN, 0);
gpio_set_level(GPIO_SUSP_VR_EN, 0);
gpio_set_level(GPIO_PP1350_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
wireless_set_state(WIRELESS_OFF);
}
}
return POWER_G3;
}
enum power_state power_handle_state(enum power_state state)
{
switch (state) {
case POWER_G3:
break;
case POWER_S5:
if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1)
return POWER_S5S3; /* Power up to next state */
break;
case POWER_S3:
/*
* If lid is closed; hold touchscreen in reset to cut power
* usage. If lid is open, take touchscreen out of reset so it
* can wake the processor. Chipset task is awakened on lid
* switch transitions.
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
/* Check for state transitions */
if (!power_has_signals(IN_PGOOD_S3)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S3S5;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
/* Power up to next state */
return POWER_S3S0;
} else if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 0) {
/* Power down to next state */
return POWER_S3S5;
}
break;
case POWER_S0:
if (!power_has_signals(IN_PGOOD_S0)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S0S3;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
/* Power down to next state */
return POWER_S0S3;
}
break;
case POWER_G3S5:
/*
* Wait 10ms after +3VALW good, since that powers VccDSW and
* VccSUS.
*/
msleep(10);
gpio_set_level(GPIO_SUSP_VR_EN, 1);
if (power_wait_signals(IN_PGOOD_S5)) {
gpio_set_level(GPIO_SUSP_VR_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
/* Deassert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 1);
/* Wait 10ms for SUSCLK to stabilize */
msleep(10);
return POWER_S5;
case POWER_S5S3:
/* Wait for the always-on rails to be good */
if (power_wait_signals(IN_PGOOD_ALWAYS_ON)) {
chipset_force_shutdown();
return POWER_S5G3;
}
/* Turn on power to RAM */
gpio_set_level(GPIO_PP1350_EN, 1);
if (power_wait_signals(IN_PGOOD_S3)) {
chipset_force_shutdown();
return POWER_S5G3;
}
/*
* Enable touchpad power so it can wake the system from
* suspend.
*/
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_STARTUP);
return POWER_S3;
case POWER_S3S0:
/* Turn on power rails */
gpio_set_level(GPIO_PP5000_EN, 1);
usleep(3 * MSEC); /* Small delay; see crosbug.com/p/25271 */
gpio_set_level(GPIO_PP3300_DX_EN, 1);
/* Enable wireless */
wireless_set_state(WIRELESS_ON);
/*
* Make sure touchscreen is out if reset (even if the lid is
* still closed); it may have been turned off if the lid was
* closed in S3.
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
/* Wait for non-core power rails good */
if (power_wait_signals(IN_PGOOD_S0)) {
chipset_force_shutdown();
wireless_set_state(WIRELESS_OFF);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
return POWER_S3;
}
/*
* Enable +CPU_CORE. The CPU itself will request the supplies
* when it's ready.
*/
gpio_set_level(GPIO_VCORE_EN, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_RESUME);
/*
* Disable idle task deep sleep. This means that the low
* power idle task will not go into deep sleep while in S0.
*/
disable_sleep(SLEEP_MASK_AP_RUN);
/*
* Wait 15 ms after all voltages good. 100 ms is only needed
* for PCIe devices; mini-PCIe devices should need only 10 ms.
*/
msleep(15);
/*
* Throttle CPU if necessary. This should only be asserted
* when +VCCP is powered (it is by now).
*/
gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
/* Set SYS and CORE PWROK */
gpio_set_level(GPIO_PCH_SYS_PWROK, 1);
gpio_set_level(GPIO_PCH_CORE_PWROK, 1);
/* Wait 50 ms for platform reset to deassert */
{
int i;
for (i = 0; i < 50; i++) {
usleep(MSEC);
if (!lpc_get_pltrst_asserted())
break;
}
if (i < 50 && !fake_pltrst_timeout) {
/* Deasserted in time */
CPRINTS("power PLTRST# deasserted");
} else {
/* Force a reset. See crosbug.com/p/28422 */
CPRINTS("power PLTRST# timeout");
power_button_pch_release();
chipset_force_shutdown();
restart_from_s5 = 1;
fake_pltrst_timeout = 0;
}
}
return POWER_S0;
case POWER_S0S3:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SUSPEND);
/* Clear SYS and CORE PWROK */
gpio_set_level(GPIO_PCH_SYS_PWROK, 0);
gpio_set_level(GPIO_PCH_CORE_PWROK, 0);
/* Wait 40ns */
udelay(1);
/* Disable +CPU_CORE */
gpio_set_level(GPIO_VCORE_EN, 0);
/* Suspend wireless */
wireless_set_state(WIRELESS_SUSPEND);
/*
* Enable idle task deep sleep. Allow the low power idle task
* to go into deep sleep in S3 or lower.
*/
enable_sleep(SLEEP_MASK_AP_RUN);
/*
* Deassert prochot since CPU is off and we're about to drop
* +VCCP.
*/
gpio_set_level(GPIO_CPU_PROCHOT, 0);
/* Turn off power rails */
msleep(7); /* Small delay; see crosbug.com/p/26561 */
gpio_set_level(GPIO_PP3300_DX_EN, 0);
#ifdef CONFIG_USB_PORT_POWER_IN_S3
/*
* Disable the 5V rail if all USB ports are disabled. Else
* leave 5V enabled so the ports will continue to work in S3.
*/
if (!usb_charge_ports_enabled())
gpio_set_level(GPIO_PP5000_EN, 0);
#else
gpio_set_level(GPIO_PP5000_EN, 0);
#endif
return POWER_S3;
case POWER_S3S5:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SHUTDOWN);
/* Turn off 5V rail (if it wasn't turned off in S3) */
gpio_set_level(GPIO_PP5000_EN, 0);
/* Disable wireless */
wireless_set_state(WIRELESS_OFF);
/* Disable touchpad power and hold touchscreen in reset */
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
/* Turn off power to RAM */
gpio_set_level(GPIO_PP1350_EN, 0);
/*
* If restarting from S5, delay and fake power button press.
* See crosbug.com/p/28422.
*/
if (restart_from_s5) {
CPRINTS("power restart from S5");
restart_from_s5 = 0;
/* Delay for system to shut down after rails dropped */
msleep(100);
/* Restart system via power button press */
power_button_pch_pulse();
/*
* Force system to start back up from scratch. This is
* needed to undo the effects of a previous call to
* chipset_force_shutdown().
*/
return POWER_G3S5;
}
/* Start shutting down */
return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
case POWER_S5G3:
/* Assert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
gpio_set_level(GPIO_SUSP_VR_EN, 0);
return POWER_G3;
}
return state;
}
static int console_command_powerfail(int argc, char **argv)
{
ccprintf("Faking a failure of next power-on event\n");
fake_pltrst_timeout = 1;
return EC_SUCCESS;
}
DECLARE_CONSOLE_COMMAND(powerfail, console_command_powerfail,
NULL,
"Fake PLTRST# failure during next power-on");

2
power/build.mk
View File

@@ -7,11 +7,9 @@
#
power-$(CONFIG_CHIPSET_APOLLOLAKE)+=apollolake.o intel_x86.o
power-$(CONFIG_CHIPSET_BAYTRAIL)+=baytrail.o
power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
power-$(CONFIG_CHIPSET_GAIA)+=gaia.o
power-$(CONFIG_CHIPSET_HASWELL)+=haswell.o
power-$(CONFIG_CHIPSET_MEDIATEK)+=mediatek.o
power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o
power-$(CONFIG_CHIPSET_ROCKCHIP)+=rockchip.o

378
power/haswell.c
View File

@@ -1,378 +0,0 @@
/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* X86 haswell chipset power control module for Chrome EC */
#include "chipset.h"
#include "common.h"
#include "console.h"
#include "ec_commands.h"
#include "gpio.h"
#include "hooks.h"
#include "lid_switch.h"
#include "power.h"
#include "system.h"
#include "timer.h"
#include "util.h"
#include "wireless.h"
/* Console output macros */
#define CPUTS(outstr) cputs(CC_CHIPSET, outstr)
#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
/* Input state flags */
#define IN_PGOOD_PP5000 POWER_SIGNAL_MASK(X86_PGOOD_PP5000)
#define IN_PGOOD_PP1350 POWER_SIGNAL_MASK(X86_PGOOD_PP1350)
#define IN_PGOOD_PP1050 POWER_SIGNAL_MASK(X86_PGOOD_PP1050)
#define IN_PGOOD_VCORE POWER_SIGNAL_MASK(X86_PGOOD_VCORE)
#define IN_SLP_S0_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S0_DEASSERTED)
#define IN_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
#define IN_SLP_S5_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S5_DEASSERTED)
#define IN_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
/* All always-on supplies */
#define IN_PGOOD_ALWAYS_ON (IN_PGOOD_PP5000)
/* All non-core power rails */
#define IN_PGOOD_ALL_NONCORE (IN_PGOOD_PP1350 | IN_PGOOD_PP1050)
/* All core power rails */
#define IN_PGOOD_ALL_CORE (IN_PGOOD_VCORE)
/* Rails required for S3 */
#define IN_PGOOD_S3 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_PP1350)
/* Rails required for S0 */
#define IN_PGOOD_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE)
/* All PM_SLP signals from PCH deasserted */
#define IN_ALL_PM_SLP_DEASSERTED (IN_SLP_S3_DEASSERTED | \
IN_SLP_S5_DEASSERTED)
/* All inputs in the right state for S0 */
#define IN_ALL_S0 (IN_PGOOD_ALWAYS_ON | IN_PGOOD_ALL_NONCORE | \
IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
static int throttle_cpu; /* Throttle CPU? */
void chipset_force_shutdown(void)
{
CPRINTS("%s()", __func__);
/*
* Force power off. This condition will reset once the state machine
* transitions to G3.
*/
gpio_set_level(GPIO_PCH_DPWROK, 0);
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
}
void chipset_reset(int cold_reset)
{
CPRINTS("%s(%d)", __func__, cold_reset);
if (cold_reset) {
/*
* Drop and restore PWROK. This causes the PCH to reboot,
* regardless of its after-G3 setting. This type of reboot
* causes the PCH to assert PLTRST#, SLP_S3#, and SLP_S5#, so
* we actually drop power to the rest of the system (hence, a
* "cold" reboot).
*/
/* Ignore if PWROK is already low */
if (gpio_get_level(GPIO_PCH_PWROK) == 0)
return;
/* PWROK must deassert for at least 3 RTC clocks = 91 us */
gpio_set_level(GPIO_PCH_PWROK, 0);
udelay(100);
gpio_set_level(GPIO_PCH_PWROK, 1);
} else {
/*
* Send a RCIN# pulse to the PCH. This just causes it to
* assert INIT# to the CPU without dropping power or asserting
* PLTRST# to reset the rest of the system. Pulse must be at
* least 16 PCI clocks long = 500 ns.
*/
/*
* The gpio pin used by the EC (PL6) does not behave in the
* correct manner when configured as open drain. In order to
* mimic open drain, the pin is initially configured as an
* input. When it is needed to drive low, the flags are
* updated which changes the pin to an output and drives the
* pin low. Note that this logic will work fine even on boards
* where RCIN# has been moved to a different pin, so there's no
* need to #ifdef this behavior. See crosbug.com/p/20173.
*/
gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_OUT_LOW);
udelay(10);
gpio_set_flags(GPIO_PCH_RCIN_L, GPIO_INPUT);
}
}
void chipset_throttle_cpu(int throttle)
{
if (chipset_in_state(CHIPSET_STATE_ON))
gpio_set_level(GPIO_CPU_PROCHOT, throttle);
}
enum power_state power_chipset_init(void)
{
/* Enable interrupts for our GPIOs */
gpio_enable_interrupt(GPIO_PCH_EDP_VDD_EN);
/*
* If we're switching between images without rebooting, see if the x86
* is already powered on; if so, leave it there instead of cycling
* through G3.
*/
if (system_jumped_to_this_image()) {
if ((power_get_signals() & IN_ALL_S0) == IN_ALL_S0) {
/* Disable idle task deep sleep when in S0. */
disable_sleep(SLEEP_MASK_AP_RUN);
CPRINTS("already in S0");
return POWER_S0;
} else {
/* Force all signals to their G3 states */
CPRINTS("forcing G3");
gpio_set_level(GPIO_PCH_PWROK, 0);
gpio_set_level(GPIO_VCORE_EN, 0);
gpio_set_level(GPIO_SUSP_VR_EN, 0);
gpio_set_level(GPIO_PP1350_EN, 0);
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_PP5000_EN, 0);
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
gpio_set_level(GPIO_PCH_DPWROK, 0);
wireless_set_state(WIRELESS_OFF);
}
}
return POWER_G3;
}
enum power_state power_handle_state(enum power_state state)
{
switch (state) {
case POWER_G3:
break;
case POWER_S5:
if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1)
return POWER_S5S3; /* Power up to next state */
break;
case POWER_S3:
/*
* If lid is closed; hold touchscreen in reset to cut power
* usage. If lid is open, take touchscreen out of reset so it
* can wake the processor. Chipset task is awakened on lid
* switch transitions.
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
/* Check for state transitions */
if (!power_has_signals(IN_PGOOD_S3)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S3S5;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
/* Power up to next state */
return POWER_S3S0;
} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
/* Power down to next state */
return POWER_S3S5;
}
break;
case POWER_S0:
if (!power_has_signals(IN_PGOOD_S0)) {
/* Required rail went away */
chipset_force_shutdown();
return POWER_S0S3;
} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
/* Power down to next state */
return POWER_S0S3;
}
break;
case POWER_G3S5:
/*
* Wait 10ms after +3VALW good, since that powers VccDSW and
* VccSUS.
*/
msleep(10);
/* Assert DPWROK */
gpio_set_level(GPIO_PCH_DPWROK, 1);
if (power_wait_signals(IN_SLP_SUS_DEASSERTED)) {
chipset_force_shutdown();
return POWER_G3;
}
gpio_set_level(GPIO_SUSP_VR_EN, 1);
if (power_wait_signals(IN_PGOOD_PP1050)) {
gpio_set_level(GPIO_SUSP_VR_EN, 0);
chipset_force_shutdown();
return POWER_G3;
}
/* Deassert RSMRST# */
gpio_set_level(GPIO_PCH_RSMRST_L, 1);
/* Wait 5ms for SUSCLK to stabilize */
msleep(5);
return POWER_S5;
case POWER_S5S3:
/* Enable PP5000 (5V) rail. */
gpio_set_level(GPIO_PP5000_EN, 1);
if (power_wait_signals(IN_PGOOD_PP5000)) {
chipset_force_shutdown();
return POWER_S5G3;
}
/* Wait for the always-on rails to be good */
if (power_wait_signals(IN_PGOOD_ALWAYS_ON)) {
chipset_force_shutdown();
return POWER_S5G3;
}
/* Turn on power to RAM */
gpio_set_level(GPIO_PP1350_EN, 1);
if (power_wait_signals(IN_PGOOD_S3)) {
chipset_force_shutdown();
return POWER_S5G3;
}
/*
* Enable touchpad power so it can wake the system from
* suspend.
*/
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_STARTUP);
return POWER_S3;
case POWER_S3S0:
/* Turn on power rails */
gpio_set_level(GPIO_PP3300_DX_EN, 1);
/* Enable wireless */
wireless_set_state(WIRELESS_ON);
/*
* Make sure touchscreen is out if reset (even if the lid is
* still closed); it may have been turned off if the lid was
* closed in S3.
*/
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
/* Wait for non-core power rails good */
if (power_wait_signals(IN_PGOOD_S0)) {
chipset_force_shutdown();
wireless_set_state(WIRELESS_OFF);
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
return POWER_S3;
}
/*
* Enable +CPU_CORE. The CPU itself will request the supplies
* when it's ready.
*/
gpio_set_level(GPIO_VCORE_EN, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_RESUME);
/*
* Disable idle task deep sleep. This means that the low
* power idle task will not go into deep sleep while in S0.
*/
disable_sleep(SLEEP_MASK_AP_RUN);
/* Wait 99ms after all voltages good */
msleep(99);
/*
* Throttle CPU if necessary. This should only be asserted
* when +VCCP is powered (it is by now).
*/
gpio_set_level(GPIO_CPU_PROCHOT, throttle_cpu);
/* Set PCH_PWROK */
gpio_set_level(GPIO_PCH_PWROK, 1);
gpio_set_level(GPIO_SYS_PWROK, 1);
return POWER_S0;
case POWER_S0S3:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SUSPEND);
/* Clear PCH_PWROK */
gpio_set_level(GPIO_SYS_PWROK, 0);
gpio_set_level(GPIO_PCH_PWROK, 0);
/* Wait 40ns */
udelay(1);
/* Disable +CPU_CORE */
gpio_set_level(GPIO_VCORE_EN, 0);
/* Suspend wireless */
wireless_set_state(WIRELESS_SUSPEND);
/*
* Enable idle task deep sleep. Allow the low power idle task
* to go into deep sleep in S3 or lower.
*/
enable_sleep(SLEEP_MASK_AP_RUN);
/*
* Deassert prochot since CPU is off and we're about to drop
* +VCCP.
*/
gpio_set_level(GPIO_CPU_PROCHOT, 0);
/* Turn off power rails */
gpio_set_level(GPIO_EC_EDP_VDD_EN, 0);
gpio_set_level(GPIO_PP3300_DX_EN, 0);
return POWER_S3;
case POWER_S3S5:
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SHUTDOWN);
/* Disable wireless */
wireless_set_state(WIRELESS_OFF);
/* Disable touchpad power */
gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
/* Turn off power to RAM */
gpio_set_level(GPIO_PP1350_EN, 0);
/* Disable PP5000 (5V) rail. */
gpio_set_level(GPIO_PP5000_EN, 0);
/* Start shutting down */
return power_get_pause_in_s5() ? POWER_S5 : POWER_S5G3;
case POWER_S5G3:
/* Deassert DPWROK, assert RSMRST# */
gpio_set_level(GPIO_PCH_DPWROK, 0);
gpio_set_level(GPIO_PCH_RSMRST_L, 0);
gpio_set_level(GPIO_SUSP_VR_EN, 0);
return POWER_G3;
}
return state;
}
void power_interrupt(enum gpio_signal signal)
{
/* Pass through eDP VDD enable from PCH */
gpio_set_level(GPIO_EC_EDP_VDD_EN, gpio_get_level(GPIO_PCH_EDP_VDD_EN));
}

2
util/flash_ec
View File

@@ -50,8 +50,6 @@ BOARDS_IT83XX=(
)
BOARDS_LM4=(
auron
rambi
samus
)