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Braswell: Turn on/off the USB power while S5->S3/S3->S5.

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The USB power is off in S5 with previous ChromeBook.
The braswell platfrom should be the same as before.

BUG=chrome-os-partner:39507
BRANCH=cyan
TEST=The usb power is off in G3/S5 and is on in S3/S0 by ec console.

Change-Id: I719f213a9eb0180f7e95e4c2717c038c79ef56fe
Signed-off-by: Henry Hsu <Henry.Hsu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/267451
Reviewed-by: Shawn N <shawnn@chromium.org>
This commit is contained in:
Hsu Henry
2015-04-27 19:36:10 +08:00
committed by ChromeOS Commit Bot
parent 3664b82294
commit d175e507d8
3 changed files with 11 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
board/cyan/gpio.inc
View File

@@ -30,7 +30,7 @@ GPIO(PCH_SCI_L, PORT(2), 6, GPIO_ODR_HIGH) /* SCI out
GPIO(NC_31, PORT(3), 1, GPIO_INPUT | GPIO_PULL_UP) /* NC */
GPIO(NC_34, PORT(3), 4, GPIO_INPUT | GPIO_PULL_UP) /* NC */
GPIO(USB2_PWR_EN, PORT(3), 6, GPIO_OUT_HIGH) /* Enable power for USB2 Port */
GPIO(USB2_PWR_EN, PORT(3), 6, GPIO_OUT_LOW) /* Enable power for USB2 Port */
GPIO(ENTERING_RW, PORT(4), 1, GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(PCH_SMI_L, PORT(4), 4, GPIO_ODR_HIGH) /* SMI output */
@@ -52,7 +52,7 @@ GPIO(BATT_EN_L, PORT(6), 2, GPIO_INPUT) /* Will be
GPIO(NC_64, PORT(6), 4, GPIO_INPUT | GPIO_PULL_UP) /* NC */
GPIO(PCH_SYS_PWROK, PORT(6), 5, GPIO_OUT_LOW) /* EC thinks everything is up and ready (DELAY_ALL_SYS_PWRGD) */
GPIO(PCH_WAKE_L, PORT(6), 6, GPIO_ODR_HIGH) /* PCH wake pin */
GPIO(USB3_PWR_EN, PORT(6), 7, GPIO_OUT_HIGH) /* Enable power for USB3 Port */
GPIO(USB3_PWR_EN, PORT(6), 7, GPIO_OUT_LOW) /* Enable power for USB3 Port */
GPIO(USB_CTL1, PORT(10), 5, GPIO_OUT_HIGH) /* USB charging mode control */

4
board/strago/gpio.inc
View File

@@ -31,7 +31,7 @@ GPIO(PCH_SCI_L, PORT(2), 6, GPIO_ODR_HIGH) /* SCI outpu
GPIO(VOLUME_UP, PORT(3), 1, GPIO_INT_FALLING) /* Volume up button */
GPIO(VOLUME_DOWN, PORT(3), 4, GPIO_INT_FALLING) /* Volume down button */
GPIO(USB2_ENABLE, PORT(3), 6, GPIO_OUT_HIGH) /* Enable power for USB2 Port */
GPIO(USB2_PWR_EN, PORT(3), 6, GPIO_OUT_LOW) /* Enable power for USB2 Port */
GPIO(ENTERING_RW, PORT(4), 1, GPIO_OUT_LOW) /* Indicate when EC is entering RW code */
GPIO(PCH_SMI_L, PORT(4), 4, GPIO_ODR_HIGH) /* SMI output */
@@ -53,7 +53,7 @@ GPIO(TEMP_SENSOR_3, PORT(6), 2, GPIO_INPUT) /* */
GPIO(USBPD_BST_OFF, PORT(6), 4, GPIO_OUT_HIGH) /* USB PD Boost Enable */
GPIO(PCH_SYS_PWROK, PORT(6), 5, GPIO_OUT_LOW) /* EC thinks everything is up and ready (DELAY_ALL_SYS_PWRGD) */
GPIO(PCH_WAKE_L, PORT(6), 6, GPIO_ODR_HIGH) /* PCH wake pin */
GPIO(USB1_ENABLE, PORT(6), 7, GPIO_OUT_HIGH) /* Enable power for USB3 Port */
GPIO(USB3_PWR_EN, PORT(6), 7, GPIO_OUT_LOW) /* Enable power for USB3 Port */
GPIO(USB_CTL1, PORT(10), 5, GPIO_OUT_HIGH) /* USB charging mode control */

7
power/braswell.c
View File

@@ -156,6 +156,9 @@ enum power_state power_handle_state(enum power_state state)
break;
case POWER_S5S3:
/* Turn on the USB power */
gpio_set_level(GPIO_USB2_PWR_EN, 1);
gpio_set_level(GPIO_USB3_PWR_EN, 1);
/* Call hooks now that rails are up */
hook_notify(HOOK_CHIPSET_STARTUP);
@@ -279,6 +282,10 @@ enum power_state power_handle_state(enum power_state state)
return POWER_S3;
case POWER_S3S5:
/* Turn off the USB power */
gpio_set_level(GPIO_USB2_PWR_EN, 0);
gpio_set_level(GPIO_USB3_PWR_EN, 0);
/* Call hooks before we remove power rails */
hook_notify(HOOK_CHIPSET_SHUTDOWN);