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Poppy: Enter/exit from S0ix based on host commands from kernel
This patch enables the entry/exit model for S0ix based on host commands. The kernel will send host events on kernel freeze/thaw exit; EC will initiate the S0ix entry based on host command and exit via another host command from kernel. BRANCH=none BUG=b:36630881 TEST=Build/flash EC and check 'echo freeze > /sys/power/state' command in OS shell. Verify EC goes to S0ix state, and on wake it comes back to S0 state. Change-Id: I22405021aead8488a5a1f166400cbde76faac59b Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Archana Patni <archana.patni@intel.com> Reviewed-on: https://chromium-review.googlesource.com/446219 Commit-Ready: Archana Patni <archana.patni@intel.corp-partner.google.com> Tested-by: Archana Patni <archana.patni@intel.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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chrome-bot
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commit
df0c0b2b33
@@ -205,7 +205,6 @@ void base_detect_interrupt(enum gpio_signal signal)
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/* power signal list. Must match order of enum power_signal. */
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const struct power_signal_info power_signal_list[] = {
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{GPIO_PCH_SLP_S0_L, 1, "SLP_S0_DEASSERTED"},
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#ifdef CONFIG_ESPI_VW_SIGNALS
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{VW_SLP_S3_L, 1, "SLP_S3_DEASSERTED"},
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{VW_SLP_S4_L, 1, "SLP_S4_DEASSERTED"},
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@@ -87,6 +87,8 @@
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#define CONFIG_POWER_BUTTON_X86
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#define CONFIG_POWER_COMMON
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#define CONFIG_POWER_SIGNAL_INTERRUPT_STORM_DETECT_THRESHOLD 30
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#define CONFIG_POWER_S0IX
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#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
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/* Sensor */
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#define CONFIG_ALS
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@@ -179,7 +181,6 @@
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#include "registers.h"
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enum power_signal {
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X86_SLP_S0_DEASSERTED,
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X86_SLP_S3_DEASSERTED,
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X86_SLP_S4_DEASSERTED,
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X86_SLP_SUS_DEASSERTED,
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@@ -10,7 +10,6 @@
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GPIO_INT(USB_C0_PD_INT_ODL, PIN(3, 7), GPIO_INT_FALLING, tcpc_alert_event)
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GPIO_INT(USB_C1_PD_INT_ODL, PIN(C, 5), GPIO_INT_FALLING, tcpc_alert_event)
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GPIO_INT(PCH_SLP_S0_L, PIN(7, 5), GPIO_INT_BOTH, power_signal_interrupt)
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/* Use VW signals instead of GPIOs */
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#ifndef CONFIG_ESPI_VW_SIGNALS
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GPIO_INT(PCH_SLP_S3_L, PIN(7, 3), GPIO_INT_BOTH, power_signal_interrupt)
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@@ -50,6 +49,7 @@ GPIO(CCD_MODE_ODL, PIN(6, 3), GPIO_INPUT) /* Case Closed Debug Mode */
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GPIO(EC_HAVEN_RESET_ODL, PIN(0, 2), GPIO_ODR_HIGH) /* H1 Reset */
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GPIO(ENTERING_RW, PIN(7, 6), GPIO_OUTPUT) /* EC Entering RW */
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GPIO(PMIC_INT_L, PIN(6, 0), GPIO_INPUT) /* PMIC interrupt */
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GPIO(PCH_SLP_S0_L, PIN(7, 5), GPIO_INPUT)
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/* Sensor interrupts, not implemented yet */
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GPIO(ALS_INT_L, PIN(2, 5), GPIO_INPUT)
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