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gma: Add flag to allow use of VGACNTRL on GMCH

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Change-Id: If2f12f14b4f367cdfc8cc2c20402f2350e3bbba8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25404
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
2018-03-28 16:42:50 +02:00
committed by Nico Huber
parent d1988d1a03
commit dfcdd77f8e
3 changed files with 12 additions and 4 deletions
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1
common/hw-gfx-gma-config.ads.template
View File

@@ -56,6 +56,7 @@ is
Has_DSP_Linoff : constant Boolean := CPU <= Ivybridge;
Has_PF_Pipe_Select : constant Boolean := CPU in Ivybridge .. Haswell;
VGA_Plane_Workaround : constant Boolean := CPU = Ivybridge;
Has_GMCH_VGACNTRL : constant Boolean := false;
----- Panel power: -----
Has_PP_Write_Protection : constant Boolean := CPU <= Ivybridge;

9
common/hw-gfx-gma-pipe_setup.adb
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@@ -89,6 +89,11 @@ package body HW.GFX.GMA.Pipe_Setup is
PS_CTRL_SCALER_MODE_7X5_EXTENDED : constant := 1 * 2 ** 28;
PS_CTRL_FILTER_SELECT_MEDIUM_2 : constant := 1 * 2 ** 23;
VGACNTRL_REG : constant Registers.Registers_Index :=
(if Config.Has_GMCH_VGACNTRL then
Registers.GMCH_VGACNTRL
else Registers.CPU_VGACNTRL);
---------------------------------------------------------------------------
function PLANE_WM_LINES (Lines : Natural) return Word32 is
@@ -260,7 +265,7 @@ package body HW.GFX.GMA.Pipe_Setup is
end if;
Registers.Unset_And_Set_Mask
(Register => Registers.VGACNTRL,
(Register => VGACNTRL_REG,
Mask_Unset => VGA_CONTROL_VGA_DISPLAY_DISABLE or
VGA_CONTROL_BLINK_DUTY_CYCLE_MASK or
VGA_CONTROL_VSYNC_BLINK_RATE_MASK,
@@ -512,7 +517,7 @@ package body HW.GFX.GMA.Pipe_Setup is
Port_IO.InB (Reg8, VGA_SR_DATA);
Port_IO.OutB (VGA_SR_DATA, Reg8 or VGA_SR01_SCREEN_OFF);
Time.U_Delay (100); -- PRM says 100us, Linux does 300
Registers.Set_Mask (Registers.VGACNTRL, VGA_CONTROL_VGA_DISPLAY_DISABLE);
Registers.Set_Mask (VGACNTRL_REG, VGA_CONTROL_VGA_DISPLAY_DISABLE);
end Legacy_VGA_Off;
procedure All_Off

6
common/hw-gfx-gma-registers.ads
View File

@@ -64,7 +64,7 @@ is
BCS_PP_DCLV_HIGH,
BCS_PP_DCLV_LOW,
GAB_CTL_REG,
VGACNTRL,
CPU_VGACNTRL,
FUSE_STATUS,
ILK_DISPLAY_CHICKEN2,
DSPCLK_GATE_D,
@@ -468,6 +468,7 @@ is
PLANE_WM_1_B_7,
PLANE_BUF_CFG_1_B,
SPBCNTR,
GMCH_VGACNTRL,
PIPE_SCANLINE_C,
PIPECCONF,
PIPECMISC,
@@ -1284,7 +1285,8 @@ is
PCH_HDMID => 16#0e_1160# / Register_Width,
-- Intel Registers
VGACNTRL => 16#04_1000# / Register_Width,
CPU_VGACNTRL => 16#04_1000# / Register_Width,
GMCH_VGACNTRL => 16#07_1400# / Register_Width,
FUSE_STATUS => 16#04_2000# / Register_Width,
FBA_CFB_BASE => 16#04_3200# / Register_Width,
IPS_CTL => 16#04_3408# / Register_Width,