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Fix clock bug on STM32F0 that HSI48 isn't enabled

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When changing the clock init code for STM32F3, I accidentally disabled
HSI48 for STM32F0, which is causing all problems on all STM32F0
platforms. Re-enable it.

BRANCH=Samus
BUG=chrome-os-partner:32660
TEST=Boot on Ryu P1 and see console.

Change-Id: Ie343cdb039d839e41b36489388fc91970e2bb7d8
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/225002
Reviewed-by: Anatol Pomazau <anatol@google.com>
Tested-by: Anatol Pomazau <anatol@google.com>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Tested-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>
This commit is contained in:
Vic Yang
2014-10-22 10:01:44 -07:00
committed by chrome-internal-fetch
parent 0907881a3a
commit e26aedecf7
1 changed files with 13 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
chip/stm32/clock-stm32f0.c
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@@ -230,7 +230,17 @@ static void config_hispeed_clock(void)
/* Wait until the PLL is the clock source */
while ((STM32_RCC_CFGR & 0xc) != 0x8)
;
#elif (CPU_CLOCK == HSI48_CLOCK)
#else
/* Ensure that HSI48 is ON */
if (!(STM32_RCC_CR2 & (1 << 17))) {
/* Enable HSI */
STM32_RCC_CR2 |= 1 << 16;
/* Wait for HSI to be ready */
while (!(STM32_RCC_CR2 & (1 << 17)))
;
}
#if (CPU_CLOCK == HSI48_CLOCK)
/*
* HSI48 = 48MHz, no prescaler, no MCO, no PLL
* therefore PCLK = FCLK = SYSCLK = 48MHz
@@ -277,7 +287,8 @@ static void config_hispeed_clock(void)
;
#else
#error "CPU_CLOCK must be either 48MHz or 38.4MHz for STM32F0"
#error "CPU_CLOCK must be either 48MHz or 38.4MHz"
#endif
#endif
}