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npcx: Move pwm open-drain functionality from gpio to pwm driver.

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Setting PWM IO type in gpio driver seems not a proper way. This
CL moves this functionality to pwm driver and introduces a new
flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it
in board driver.

BRANCH=none
BUG=none
TEST=test pwm functionality on npcx_evb.

Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/458043
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Mulin Chao
2017-03-22 17:42:34 +08:00
committed by chrome-bot
parent 61f61b368e
commit e43ba03ebf
7 changed files with 18 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/npcx_evb/board.c
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@@ -45,7 +45,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/******************************************************************************/
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
[PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP, 100},
[PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN, 100},
[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);

8
board/npcx_evb/gpio.inc
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@@ -70,14 +70,14 @@ ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA/I2C3SCL
ALTERNATE(PIN_MASK(4, 0x38), 1, MODULE_ADC, 0) /* ADC GPIO45/44/43 */
ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */
ALTERNATE(PIN_MASK(C, 0x04), 3, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
ALTERNATE(PIN_MASK(C, 0x04), 1, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
/* Alternative functionality for FANS */
#ifdef CONFIG_FANS
ALTERNATE(PIN_MASK(C, 0x08), 7, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
#if NPCX_TACH_SEL2
ALTERNATE(PIN_MASK(9, 0x08), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
#else
ALTERNATE(PIN_MASK(4, 0x01), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
#endif
#endif

2
board/npcx_evb_arm/board.c
View File

@@ -45,7 +45,7 @@ BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
/******************************************************************************/
/* PWM channels. Must be in the exactly same order as in enum pwm_channel. */
const struct pwm_t pwm_channels[] = {
[PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP, 100},
[PWM_CH_FAN] = { 0, PWM_CONFIG_DSLEEP | PWM_CONFIG_OPEN_DRAIN, 100},
[PWM_CH_KBLIGHT] = { 1, 0, 10000 },
};
BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);

8
board/npcx_evb_arm/gpio.inc
View File

@@ -71,14 +71,14 @@ ALTERNATE(PIN_MASK(D, 0x03), 1, MODULE_I2C, 0) /* I2C3SDA/I2C3SCL
ALTERNATE(PIN_MASK(4, 0x38), 1, MODULE_ADC, 0) /* ADC GPIO45/44/43 */
ALTERNATE(PIN_MASK(A, 0x0A), 1, MODULE_SPI, 0) /* SPIP_MOSI/SPIP_SCLK GPIOA3/A1 */
ALTERNATE(PIN_MASK(9, 0x20), 1, MODULE_SPI, 0) /* SPIP_MISO GPIO95 */
ALTERNATE(PIN_MASK(C, 0x04), 3, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
ALTERNATE(PIN_MASK(C, 0x04), 1, MODULE_PWM, 0) /* PWM1 for PWM/KBLIGHT Test GPIOC2 */
/* Alternative functionality for FANS */
#ifdef CONFIG_FANS
ALTERNATE(PIN_MASK(C, 0x08), 7, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
ALTERNATE(PIN_MASK(C, 0x08), 1, MODULE_PWM, 0) /* PWM0 for PWM/FAN Test GPIOC3 */
#if NPCX_TACH_SEL2
ALTERNATE(PIN_MASK(9, 0x08), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
ALTERNATE(PIN_MASK(9, 0x08), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN GPIO93 */
#else
ALTERNATE(PIN_MASK(4, 0x01), 3, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
ALTERNATE(PIN_MASK(4, 0x01), 1, MODULE_PWM, 0) /* MFT-1/TA1_TACH1 for FAN Test GPIO40 */
#endif
#endif

18
chip/npcx/gpio.c
View File

@@ -34,10 +34,6 @@ static const struct npcx_wui gpio_wui_table[] = {
#include "gpio.wrap"
};
/* Flags for PWM IO type */
#define PWM_IO_FUNC (1 << 1) /* PWM optional func bit */
#define PWM_IO_OD (1 << 2) /* PWM IO open-drain bit */
struct npcx_gpio {
uint8_t port : 4;
uint8_t bit : 3;
@@ -199,16 +195,6 @@ static int gpio_match(uint8_t port, uint8_t mask, struct npcx_gpio gpio)
return (gpio.valid && (gpio.port == port) && ((1 << gpio.bit) == mask));
}
static void gpio_pwm_io_type_sel(uint8_t chan, uint8_t func)
{
if (func & PWM_IO_OD)
/* Set PWM open drain output is open drain type*/
SET_BIT(NPCX_PWMCTLEX(chan), NPCX_PWMCTLEX_OD_OUT);
else
/* Set PWM open drain output is push-pull type*/
CLEAR_BIT(NPCX_PWMCTLEX(chan), NPCX_PWMCTLEX_OD_OUT);
}
static int gpio_alt_sel(uint8_t port, uint8_t bit, int8_t func)
{
struct gpio_alt_map const *map;
@@ -228,10 +214,6 @@ static int gpio_alt_sel(uint8_t port, uint8_t bit, int8_t func)
else
NPCX_DEVALT(map->alt.group) |= alt_mask;
/* PWM optional functionality */
if ((func >= 0) && (func & PWM_IO_FUNC))
gpio_pwm_io_type_sel(map->alt.bit, func);
return 1;
}
}

4
chip/npcx/pwm.c
View File

@@ -223,6 +223,10 @@ void pwm_config(enum pwm_channel ch)
UPDATE_BIT(NPCX_PWMCTL(mdl), NPCX_PWMCTL_CKSEL,
(pwm_channels[ch].flags & PWM_CONFIG_DSLEEP));
/* Select PWM IO type */
UPDATE_BIT(NPCX_PWMCTLEX(mdl), NPCX_PWMCTLEX_OD_OUT,
(pwm_channels[ch].flags & PWM_CONFIG_OPEN_DRAIN));
/* Set PWM operation frequency */
pwm_set_freq(ch, pwm_channels[ch].freq);
}

4
include/pwm.h
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@@ -71,4 +71,8 @@ int pwm_get_duty(enum pwm_channel ch);
* PWM channel must stay active in low-power idle, if enabled.
*/
#define PWM_CONFIG_DSLEEP (1 << 4)
/**
* PWM channel's IO type is open-drain, if enabled. (default IO is push-pull.)
*/
#define PWM_CONFIG_OPEN_DRAIN (1 << 5)
#endif /* __CROS_EC_PWM_H */