mirror of
https://github.com/Telecominfraproject/OpenCellular.git
synced 2025-12-28 10:45:22 +00:00
Expose and augment parser enum and field name tables to bct_dump.
This adds the nvbctlib id value to the field_item struct and makes the parser tables available outside of parse.c. This lets bct_dump use these to pretty print a BCT in a format that the parser can later read back in. BUG=chromium-os:11981 TEST=Sign and boot a U-Boot image on Seaboard using: sudo emerge -av cbootimage USE="recovery flasher" emerge-tegra2_seaboard -av chromeos-u-boot-next cros_write_firmware --board tegra2_seaboard --firmware /build/tegra2_seaboard/u-boot/u-boot-recovery.bin --sign Change-Id: Ibcc8ce5c2c62cbfea8ca2850ddd8122b84c0f78f Review URL: http://codereview.chromium.org/6677007
This commit is contained in:
Anton Staaf
@@ -28,6 +28,7 @@ cbootimage: $(CBOOTIMAGE_OBJS)
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BCT_DUMP_C_FILES := bct_dump.c
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BCT_DUMP_C_FILES += nvbctlib_ap20.c
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BCT_DUMP_C_FILES += data_layout.c
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BCT_DUMP_C_FILES += parse.c
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BCT_DUMP_C_FILES += set.c
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BCT_DUMP_C_FILES += crypto.c
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BCT_DUMP_C_FILES += aes_ref.c
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338
bct_dump.c
338
bct_dump.c
@@ -24,6 +24,7 @@
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#include "nvbctlib.h"
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#include "data_layout.h"
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#include "context.h"
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#include "parse.h"
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#include <string.h>
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@@ -78,240 +79,66 @@ static value_data const bl_values[] = {
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" Attributes....: 0x%08x\n"},
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};
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static value_data const spi_values[] = {
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{nvbct_lib_id_spiflash_read_command_type_fast,
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" Command fast...: %d\n"},
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{nvbct_lib_id_spiflash_clock_source,
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" Clock source...: %d\n"},
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{nvbct_lib_id_spiflash_clock_divider,
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" Clock divider..: %d\n"},
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};
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static value_data const sdmmc_values[] = {
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{nvbct_lib_id_sdmmc_clock_divider,
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" Clock divider..: %d\n"},
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{nvbct_lib_id_sdmmc_data_width,
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" Data width.....: %d\n"},
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{nvbct_lib_id_sdmmc_max_power_class_supported,
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" Power class....: %d\n"},
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};
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static value_data const sdram_values[] = {
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{nvbct_lib_id_sdram_pllm_charge_pump_setup_ctrl,
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" PLLM_CHARGE_PUMP_SETUP_CTRL.....: 0x%08x\n"},
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{nvbct_lib_id_sdram_pllm_loop_filter_setup_ctrl,
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" PLLM_LOOP_FILTER_SETUP_CTRL.....: 0x%08x\n"},
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{nvbct_lib_id_sdram_pllm_input_divider,
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" PLLM_INPUT_DIVIDER..............: 0x%08x\n"},
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{nvbct_lib_id_sdram_pllm_feedback_divider,
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" PLLM_FEEDBACK_DIVIDER...........: 0x%08x\n"},
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{nvbct_lib_id_sdram_pllm_post_divider,
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" PLLM_POST_DIVIDER...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_pllm_stable_time,
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" PLLM_STABLE_TIME................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_clock_divider,
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" EMC_CLOCK_DIVIDER...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_auto_cal_interval,
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" EMC_AUTO_CAL_INTERVAL...........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_auto_cal_config,
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" EMC_AUTO_CAL_CONFIG.............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_auto_cal_wait,
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" EMC_AUTO_CAL_WAIT...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_pin_program_wait,
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" EMC_PIN_PROGRAM_WAIT............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rc,
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" EMC_RC..........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rfc,
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" EMC_RFC.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_ras,
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" EMC_RAS.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rp,
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" EMC_RP..........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_r2w,
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" EMC_R2W.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_w2r,
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" EMC_W2R.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_r2p,
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" EMC_R2P.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_w2p,
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" EMC_W2P.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rd_rcd,
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" EMC_RD_RCD......................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_wr_rcd,
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" EMC_WR_RCD......................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rrd,
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" EMC_RRD.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rext,
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" EMC_REXT........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_wdv,
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" EMC_WDV.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_quse,
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" EMC_QUSE........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_qrst,
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" EMC_QRST........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_qsafe,
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" EMC_QSAFE.......................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rdv,
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" EMC_RDV.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_refresh,
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" EMC_REFRESH.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_burst_refresh_num,
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" EMC_BURST_REFRESH_NUM...........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_pdex2wr,
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" EMC_PDEX2WR.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_pdex2rd,
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" EMC_PDEX2RD.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_pchg2pden,
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" EMC_PCHG2PDEN...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_act2pden,
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" EMC_ACT2PDEN....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_ar2pden,
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" EMC_AR2PDEN.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_rw2pden,
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" EMC_RW2PDEN.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_txsr,
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" EMC_TXSR........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_tcke,
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" EMC_TCKE........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_tfaw,
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" EMC_TFAW........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_trpab,
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" EMC_TRPAB.......................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_tclkstable,
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" EMC_TCLKSTABLE..................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_tclkstop,
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" EMC_TCLKSTOP....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_trefbw,
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" EMC_TREFBW......................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_quse_extra,
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" EMC_QUSE_EXTRA..................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_cfg1,
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" EMC_FBIO_CFG1...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_dqsib_dly,
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" EMC_FBIO_DQSIB_DLY..............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_dqsib_dly_msb,
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" EMC_FBIO_DQSIB_DLY_MSB..........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_quse_dly,
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" EMC_FBIO_QUSE_DLY...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_quse_dly_msb,
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" EMC_FBIO_QUSE_DLY_MSB...........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_cfg5,
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" EMC_FBIO_CFG5...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_cfg6,
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" EMC_FBIO_CFG6...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_fbio_spare,
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" EMC_FBIO_SPARE..................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrs,
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" EMC_MRS.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_emrs,
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" EMC_EMRS........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw1,
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" EMC_MRW1........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw2,
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" EMC_MRW2........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw3,
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" EMC_MRW3........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw_reset_command,
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" EMC_MRW_RESET_COMMAND...........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw_reset_ninit_wait,
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" EMC_MRW_RESET_NINIT_WAIT........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_adr_cfg,
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" EMC_ADR_CFG.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_adr_cfg1,
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" EMC_ADR_CFG1....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_mc_emem_Cfg,
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" MC_EMEM_CFG.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_mc_lowlatency_config,
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" MC_LOWLATENCY_CONFIG............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_cfg,
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" EMC_CFG.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_cfg2,
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" EMC_CFG2........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_dbg,
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" EMC_DBG.........................: 0x%08x\n"},
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{nvbct_lib_id_sdram_ahb_arbitration_xbar_ctrl,
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" AHB_ARBITRATION_XBAR_CTRL.......: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_cfg_dig_dll,
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" EMC_CFG_DIG_DLL.................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_dll_xform_dqs,
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" EMC_DLL_XFORM_DQS...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_dll_xform_quse,
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" EMC_DLL_XFORM_QUSE..............: 0x%08x\n"},
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{nvbct_lib_id_sdram_warm_boot_wait,
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" WARM_BOOT_WAIT..................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_ctt_term_ctrl,
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" EMC_CTT_TERM_CTRL...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_odt_write,
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" EMC_ODT_WRITE...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_odt_read,
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" EMC_ODT_READ....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_zcal_ref_cnt,
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" EMC_ZCAL_REF_CNT................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_zcal_wait_cnt,
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" EMC_ZCAL_WAIT_CNT...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_zcal_mrw_cmd,
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" EMC_ZCAL_MRW_CMD................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrs_reset_dll,
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" EMC_MRS_RESET_DLL...............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw_zq_init_dev0,
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" EMC_MRW_ZQ_INIT_DEV0............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw_zq_init_dev1,
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" EMC_MRW_ZQ_INIT_DEV1............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrw_zq_init_wait,
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" EMC_MRW_ZQ_INIT_WAIT............: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrs_reset_dll_wait,
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" EMC_MRS_RESET_DLL_WAIT..........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_emrs_emr2,
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" EMC_EMRS_EMR2...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_emrs_emr3,
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" EMC_EMRS_EMR3...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_emrs_ddr2_dll_enable,
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" EMC_EMRS_DDR2_DLL_ENABLE........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_mrs_ddr2_dll_reset,
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" EMC_MRS_DDR2_DLL_RESET..........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_emrs_ddr2_ocd_calib,
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" EMC_EMRS_DDR2_OCD_CALIB.........: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_ddr2_wait,
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" EMC_DDR2_WAIT...................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_cfg_clktrim0,
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" EMC_CFG_CLKTRIM0................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_cfg_clktrim1,
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" EMC_CFG_CLKTRIM1................: 0x%08x\n"},
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{nvbct_lib_id_sdram_emc_cfg_clktrim2,
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" EMC_CFG_CLKTRIM2................: 0x%08x\n"},
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{nvbct_lib_id_sdram_pmc_ddr_pwr,
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" PMC_DDR_PWR.....................: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2cfga_pad_ctrl,
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" APB_MISC_GP_XM2CFGA_PAD_CTRL....: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl,
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" APB_MISC_GP_XM2CFGC_PAD_CTRL....: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2cfgc_pad_ctrl2,
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" APB_MISC_GP_XM2CFGC_PAD_CTRL2...: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl,
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" APB_MISC_GP_XM2CFGD_PAD_CTRL....: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2cfgd_pad_ctrl2,
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" APB_MISC_GP_XM2CFGD_PAD_CTRL2...: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2clkcfg_Pad_ctrl,
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" APB_MISC_GP_XM2CLKCFG_PAD_CTRL..: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2comp_pad_ctrl,
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" APB_MISC_GP_XM2COMP_PAD_CTRL....: 0x%08x\n"},
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{nvbct_lib_id_sdram_apb_misc_gp_xm2vttgen_pad_ctrl,
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" APB_MISC_GP_XM2VTTGEN_PAD_CTRL..: 0x%08x\n"},
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};
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static const char *sdram_types[nvboot_memory_type_num] = {
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"None", "DDR", "LPDDR", "DDR2", "LPDDR2"
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};
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static void
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usage(void)
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/*****************************************************************************/
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static void usage(void)
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{
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printf("Usage: bct_dump bctfile\n");
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printf(" bctfile BCT filename to read and display\n");
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}
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/*****************************************************************************/
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static int max_width(field_item const * table)
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{
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int width = 0;
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int i;
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int
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main(int argc, char *argv[])
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for (i = 0; table[i].name != NULL; ++i)
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{
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int length = strlen(table[i].name);
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if (width < length)
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width = length;
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}
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return width;
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}
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/*****************************************************************************/
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static int display_field_value(field_item const * item, u_int32_t value)
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{
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switch (item->type)
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{
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case field_type_enum:
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/*
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* It would be ideal if we could take the enum value
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* and programatically look up a string that the parse
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* would accept for this field. The problem is that
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* the mapping between field values and nvbct_lib_id
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* values is hard coded in the nvbctlib source. For
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* now we drop down to the u32 printing code.
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*
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* TODO(robotboy): Fix this
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*/
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case field_type_u32:
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printf("0x%08x", value);
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break;
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case field_type_u8:
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printf("0x%02x", value);
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break;
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default:
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printf("<UNKNOWN FIELD TYPE (%d)>", item->type);
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return 1;
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}
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return 0;
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}
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/*****************************************************************************/
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int main(int argc, char *argv[])
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{
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int e;
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build_image_context context;
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@@ -322,8 +149,6 @@ main(int argc, char *argv[])
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u_int32_t data;
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int i;
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int j;
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value_data const * device_values;
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int device_count;
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if (argc != 2)
|
||||
usage();
|
||||
@@ -372,6 +197,9 @@ main(int argc, char *argv[])
|
||||
context.bct);
|
||||
|
||||
for (i = 0; (e == 0) && (i < parameters_used); ++i) {
|
||||
field_item const * device_field_table = NULL;
|
||||
field_item const * item;
|
||||
|
||||
printf("DeviceParameter[%d]\n", i);
|
||||
|
||||
e = context.bctlib.getdev_param(i,
|
||||
@@ -382,35 +210,40 @@ main(int argc, char *argv[])
|
||||
switch (type)
|
||||
{
|
||||
case nvboot_dev_type_spi:
|
||||
printf(" Type...........: SPI\n");
|
||||
device_values = spi_values;
|
||||
device_count = (sizeof(spi_values) /
|
||||
sizeof(spi_values[0]));
|
||||
printf(" Type = SPI\n");
|
||||
device_field_table = s_spiflash_table;
|
||||
break;
|
||||
|
||||
case nvboot_dev_type_sdmmc:
|
||||
printf(" Type...........: SDMMC\n");
|
||||
device_values = sdmmc_values;
|
||||
device_count = (sizeof(sdmmc_values) /
|
||||
sizeof(sdmmc_values[0]));
|
||||
printf(" Type = SDMMC\n");
|
||||
device_field_table = s_sdmmc_table;
|
||||
break;
|
||||
|
||||
case nvboot_dev_type_nand:
|
||||
printf(" Type = NAND\n");
|
||||
device_field_table = s_nand_table;
|
||||
break;
|
||||
|
||||
default:
|
||||
printf(" Type...........: Unknown (%d)\n",
|
||||
device_field_table = NULL;
|
||||
printf(" Type = <UNKNOWN TYPE (%d)>\n",
|
||||
type);
|
||||
device_values = NULL;
|
||||
device_count = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
for (j = 0; j < device_count; ++j) {
|
||||
value_data value = device_values[j];
|
||||
if (!device_field_table)
|
||||
continue;
|
||||
|
||||
int width = max_width(device_field_table);
|
||||
|
||||
for (item = device_field_table; item->name != NULL; ++item) {
|
||||
e = context.bctlib.getdev_param(i,
|
||||
value.id,
|
||||
item->enum_value,
|
||||
&data,
|
||||
context.bct);
|
||||
printf(value.message, e == 0 ? data : -1);
|
||||
printf(" %-*s = 0x%08x\n",
|
||||
width, item->name,
|
||||
e == 0 ? data : -1);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -431,13 +264,22 @@ main(int argc, char *argv[])
|
||||
type < nvboot_memory_type_num ? sdram_types[type]
|
||||
: "Unknown");
|
||||
|
||||
for (j = 0; j < sizeof(sdram_values) / sizeof(sdram_values[0]);
|
||||
++j) {
|
||||
int width = max_width(s_sdram_field_table);
|
||||
field_item const * item;
|
||||
|
||||
for (item = s_sdram_field_table; item->name != NULL; ++item) {
|
||||
e = context.bctlib.get_sdram_params(i,
|
||||
sdram_values[j].id,
|
||||
&data,
|
||||
context.bct);
|
||||
printf(sdram_values[j].message, e == 0 ? data : -1);
|
||||
item->enum_value,
|
||||
&data,
|
||||
context.bct);
|
||||
printf(" %-*s = ", width, item->name);
|
||||
|
||||
if (e != 0)
|
||||
printf("<ERROR reading parameter (%d)>", e);
|
||||
else
|
||||
display_field_value(item, data);
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
383
parse.c
383
parse.c
@@ -61,7 +61,7 @@ static char *parse_enum(build_image_context *context,
|
||||
static char
|
||||
*parse_field_name(char *rest, field_item *field_table, field_item **field);
|
||||
static char
|
||||
*parse_field_value(build_image_context *context,
|
||||
*parse_field_value(build_image_context *context,
|
||||
char *rest,
|
||||
field_item *field,
|
||||
u_int32_t *value);
|
||||
@@ -85,7 +85,7 @@ parse_sdram_param(build_image_context *context, parse_token token, char *rest);
|
||||
|
||||
static int process_statement(build_image_context *context, char *statement);
|
||||
|
||||
static enum_item s_devtype_table[] =
|
||||
enum_item s_devtype_table[] =
|
||||
{
|
||||
{ "NvBootDevType_Sdmmc", nvbct_lib_id_dev_type_sdmmc },
|
||||
{ "NvBootDevType_Spi", nvbct_lib_id_dev_type_spi },
|
||||
@@ -97,7 +97,7 @@ static enum_item s_devtype_table[] =
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
static enum_item s_sdmmc_data_width_table[] =
|
||||
enum_item s_sdmmc_data_width_table[] =
|
||||
{
|
||||
{
|
||||
"NvBootSdmmcDataWidth_4Bit",
|
||||
@@ -112,7 +112,7 @@ static enum_item s_sdmmc_data_width_table[] =
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
static enum_item s_spi_clock_source_table[] =
|
||||
enum_item s_spi_clock_source_table[] =
|
||||
{
|
||||
{
|
||||
"NvBootSpiClockSource_PllPOut0",
|
||||
@@ -145,7 +145,7 @@ static enum_item s_spi_clock_source_table[] =
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
static enum_item s_nvboot_memory_type_table[] =
|
||||
enum_item s_nvboot_memory_type_table[] =
|
||||
{
|
||||
{ "NvBootMemoryType_None", nvbct_lib_id_memory_type_none },
|
||||
{ "NvBootMemoryType_Ddr2", nvbct_lib_id_memory_type_ddr2 },
|
||||
@@ -162,247 +162,164 @@ static enum_item s_nvboot_memory_type_table[] =
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
static field_item s_sdram_field_table[] =
|
||||
{
|
||||
{ "MemoryType", token_memory_type,
|
||||
field_type_enum, s_nvboot_memory_type_table },
|
||||
{ "PllMChargePumpSetupControl", token_pllm_charge_pump_setup_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "PllMLoopFilterSetupControl", token_pllm_loop_filter_setup_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "PllMInputDivider", token_pllm_input_divider,
|
||||
field_type_u32, NULL },
|
||||
{ "PllMFeedbackDivider", token_pllm_feedback_divider,
|
||||
field_type_u32, NULL },
|
||||
{ "PllMPostDivider", token_pllm_post_divider,
|
||||
field_type_u32, NULL },
|
||||
{ "PllMStableTime", token_pllm_stable_time,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcClockDivider", token_emc_clock_divider,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAutoCalInterval", token_emc_auto_cal_interval,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAutoCalConfig", token_emc_auto_cal_config,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAutoCalWait", token_emc_auto_cal_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcPinProgramWait", token_emc_pin_program_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRc", token_emc_rc,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRfc", token_emc_rfc,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRas", token_emc_ras,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRp", token_emc_rp,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcR2w", token_emc_r2w,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcW2r", token_emc_w2r,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcR2p", token_emc_r2p,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcW2p", token_emc_w2p,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRrd", token_emc_rrd,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRdRcd", token_emc_rd_rcd,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcWrRcd", token_emc_wr_rcd,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRext", token_emc_rext,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcWdv", token_emc_wdv,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcQUseExtra", token_emc_quse_extra,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcQUse", token_emc_quse,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcQRst", token_emc_qrst,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcQSafe", token_emc_qsafe,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRdv", token_emc_rdv,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRefresh", token_emc_refresh,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcBurstRefreshNum", token_emc_burst_refresh_num,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcPdEx2Wr", token_emc_pdex2wr,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcPdEx2Rd", token_emc_pdex2rd,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcPChg2Pden", token_emc_pchg2pden,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAct2Pden", token_emc_act2pden,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAr2Pden", token_emc_ar2pden,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcRw2Pden", token_emc_rw2pden,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTxsr", token_emc_txsr,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTcke", token_emc_tcke,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTfaw", token_emc_tfaw,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTrpab", token_emc_trpab,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTClkStable", token_emc_tclkstable,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTClkStop", token_emc_tclkstop,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcTRefBw", token_emc_trefbw,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioCfg1", token_emc_fbio_cfg1,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioDqsibDlyMsb", token_emc_fbio_dqsib_dly_msb,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioDqsibDly", token_emc_fbio_dqsib_dly,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioQuseDlyMsb", token_emc_fbio_quse_dly_msb,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioQuseDly", token_emc_fbio_quse_dly,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioCfg5", token_emc_fbio_cfg5,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioCfg6", token_emc_fbio_cfg6,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcFbioSpare", token_emc_fbio_spare,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrsResetDllWait", token_emc_mrs_reset_dll_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrsResetDll", token_emc_mrs_reset_dll,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrsDdr2DllReset", token_emc_mrs_ddr2_dll_reset,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrs", token_emc_mrs,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcEmrsEmr2", token_emc_emrs_emr2,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcEmrsEmr3", token_emc_emrs_emr3,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcEmrsDdr2DllEnable", token_emc_emrs_ddr2_dll_enable,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcEmrsDdr2OcdCalib", token_emc_emrs_ddr2_ocd_calib,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcEmrs", token_emc_emrs,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrw1", token_emc_mrw1,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrw2", token_emc_mrw2,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrw3", token_emc_mrw3,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrwResetCommand", token_emc_mrw_reset_command,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrwResetNInitWait", token_emc_mrw_reset_ninit_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAdrCfg1", token_emc_adr_cfg1,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcAdrCfg", token_emc_adr_cfg,
|
||||
field_type_u32, NULL },
|
||||
{ "McEmemCfg", token_mc_emem_Cfg,
|
||||
field_type_u32, NULL },
|
||||
{ "McLowLatencyConfig", token_mc_lowlatency_config,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCfg2", token_emc_cfg2,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCfgDigDll", token_emc_cfg_dig_dll,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCfgClktrim0", token_emc_cfg_clktrim0,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCfgClktrim1", token_emc_cfg_clktrim1,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCfgClktrim2", token_emc_cfg_clktrim2,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCfg", token_emc_cfg,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcDbg", token_emc_dbg,
|
||||
field_type_u32, NULL },
|
||||
{ "AhbArbitrationXbarCtrl", token_ahb_arbitration_xbar_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcDllXformDqs", token_emc_dll_xform_dqs,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcDllXformQUse", token_emc_dll_xform_quse,
|
||||
field_type_u32, NULL },
|
||||
{ "WarmBootWait", token_warm_boot_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcCttTermCtrl", token_emc_ctt_term_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcOdtWrite", token_emc_odt_write,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcOdtRead", token_emc_odt_read,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcZcalRefCnt", token_emc_zcal_ref_cnt,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcZcalWaitCnt", token_emc_zcal_wait_cnt,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcZcalMrwCmd", token_emc_zcal_mrw_cmd,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrwZqInitDev0", token_emc_mrw_zq_init_dev0,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrwZqInitDev1", token_emc_mrw_zq_init_dev1,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcMrwZqInitWait", token_emc_mrw_zq_init_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "EmcDdr2Wait", token_emc_ddr2_wait,
|
||||
field_type_u32, NULL },
|
||||
{ "PmcDdrPwr", token_pmc_ddr_pwr,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2CfgAPadCtrl", token_apb_misc_gp_xm2cfga_pad_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2CfgCPadCtrl2", token_apb_misc_gp_xm2cfgc_pad_ctrl2,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2CfgCPadCtrl", token_apb_misc_gp_xm2cfgc_pad_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2CfgDPadCtrl2", token_apb_misc_gp_xm2cfgd_pad_ctrl2,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2CfgDPadCtrl", token_apb_misc_gp_xm2cfgd_pad_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2ClkCfgPadCtrl", token_apb_misc_gp_xm2clkcfg_Pad_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2CompPadCtrl", token_apb_misc_gp_xm2comp_pad_ctrl,
|
||||
field_type_u32, NULL },
|
||||
{ "ApbMiscGpXm2VttGenPadCtrl", token_apb_misc_gp_xm2vttgen_pad_ctrl
|
||||
,field_type_u32, NULL },
|
||||
#define TOKEN(name) \
|
||||
token_##name, nvbct_lib_id_sdram_##name, field_type_u32, NULL
|
||||
|
||||
{ NULL, 0, 0, NULL }
|
||||
field_item s_sdram_field_table[] =
|
||||
{
|
||||
{ "MemoryType", token_memory_type, nvbct_lib_id_sdram_memory_type,
|
||||
field_type_enum, s_nvboot_memory_type_table },
|
||||
|
||||
{ "PllMChargePumpSetupControl", TOKEN(pllm_charge_pump_setup_ctrl) },
|
||||
{ "PllMLoopFilterSetupControl", TOKEN(pllm_loop_filter_setup_ctrl) },
|
||||
{ "PllMInputDivider", TOKEN(pllm_input_divider) },
|
||||
{ "PllMFeedbackDivider", TOKEN(pllm_feedback_divider) },
|
||||
{ "PllMPostDivider", TOKEN(pllm_post_divider) },
|
||||
{ "PllMStableTime", TOKEN(pllm_stable_time) },
|
||||
{ "EmcClockDivider", TOKEN(emc_clock_divider) },
|
||||
{ "EmcAutoCalInterval", TOKEN(emc_auto_cal_interval) },
|
||||
{ "EmcAutoCalConfig", TOKEN(emc_auto_cal_config) },
|
||||
{ "EmcAutoCalWait", TOKEN(emc_auto_cal_wait) },
|
||||
{ "EmcPinProgramWait", TOKEN(emc_pin_program_wait) },
|
||||
{ "EmcRc", TOKEN(emc_rc) },
|
||||
{ "EmcRfc", TOKEN(emc_rfc) },
|
||||
{ "EmcRas", TOKEN(emc_ras) },
|
||||
{ "EmcRp", TOKEN(emc_rp) },
|
||||
{ "EmcR2w", TOKEN(emc_r2w) },
|
||||
{ "EmcW2r", TOKEN(emc_w2r) },
|
||||
{ "EmcR2p", TOKEN(emc_r2p) },
|
||||
{ "EmcW2p", TOKEN(emc_w2p) },
|
||||
{ "EmcRrd", TOKEN(emc_rrd) },
|
||||
{ "EmcRdRcd", TOKEN(emc_rd_rcd) },
|
||||
{ "EmcWrRcd", TOKEN(emc_wr_rcd) },
|
||||
{ "EmcRext", TOKEN(emc_rext) },
|
||||
{ "EmcWdv", TOKEN(emc_wdv) },
|
||||
{ "EmcQUseExtra", TOKEN(emc_quse_extra) },
|
||||
{ "EmcQUse", TOKEN(emc_quse) },
|
||||
{ "EmcQRst", TOKEN(emc_qrst) },
|
||||
{ "EmcQSafe", TOKEN(emc_qsafe) },
|
||||
{ "EmcRdv", TOKEN(emc_rdv) },
|
||||
{ "EmcRefresh", TOKEN(emc_refresh) },
|
||||
{ "EmcBurstRefreshNum", TOKEN(emc_burst_refresh_num) },
|
||||
{ "EmcPdEx2Wr", TOKEN(emc_pdex2wr) },
|
||||
{ "EmcPdEx2Rd", TOKEN(emc_pdex2rd) },
|
||||
{ "EmcPChg2Pden", TOKEN(emc_pchg2pden) },
|
||||
{ "EmcAct2Pden", TOKEN(emc_act2pden) },
|
||||
{ "EmcAr2Pden", TOKEN(emc_ar2pden) },
|
||||
{ "EmcRw2Pden", TOKEN(emc_rw2pden) },
|
||||
{ "EmcTxsr", TOKEN(emc_txsr) },
|
||||
{ "EmcTcke", TOKEN(emc_tcke) },
|
||||
{ "EmcTfaw", TOKEN(emc_tfaw) },
|
||||
{ "EmcTrpab", TOKEN(emc_trpab) },
|
||||
{ "EmcTClkStable", TOKEN(emc_tclkstable) },
|
||||
{ "EmcTClkStop", TOKEN(emc_tclkstop) },
|
||||
{ "EmcTRefBw", TOKEN(emc_trefbw) },
|
||||
{ "EmcFbioCfg1", TOKEN(emc_fbio_cfg1) },
|
||||
{ "EmcFbioDqsibDlyMsb", TOKEN(emc_fbio_dqsib_dly_msb) },
|
||||
{ "EmcFbioDqsibDly", TOKEN(emc_fbio_dqsib_dly) },
|
||||
{ "EmcFbioQuseDlyMsb", TOKEN(emc_fbio_quse_dly_msb) },
|
||||
{ "EmcFbioQuseDly", TOKEN(emc_fbio_quse_dly) },
|
||||
{ "EmcFbioCfg5", TOKEN(emc_fbio_cfg5) },
|
||||
{ "EmcFbioCfg6", TOKEN(emc_fbio_cfg6) },
|
||||
{ "EmcFbioSpare", TOKEN(emc_fbio_spare) },
|
||||
{ "EmcMrsResetDllWait", TOKEN(emc_mrs_reset_dll_wait) },
|
||||
{ "EmcMrsResetDll", TOKEN(emc_mrs_reset_dll) },
|
||||
{ "EmcMrsDdr2DllReset", TOKEN(emc_mrs_ddr2_dll_reset) },
|
||||
{ "EmcMrs", TOKEN(emc_mrs) },
|
||||
{ "EmcEmrsEmr2", TOKEN(emc_emrs_emr2) },
|
||||
{ "EmcEmrsEmr3", TOKEN(emc_emrs_emr3) },
|
||||
{ "EmcEmrsDdr2DllEnable", TOKEN(emc_emrs_ddr2_dll_enable) },
|
||||
{ "EmcEmrsDdr2OcdCalib", TOKEN(emc_emrs_ddr2_ocd_calib) },
|
||||
{ "EmcEmrs", TOKEN(emc_emrs) },
|
||||
{ "EmcMrw1", TOKEN(emc_mrw1) },
|
||||
{ "EmcMrw2", TOKEN(emc_mrw2) },
|
||||
{ "EmcMrw3", TOKEN(emc_mrw3) },
|
||||
{ "EmcMrwResetCommand", TOKEN(emc_mrw_reset_command) },
|
||||
{ "EmcMrwResetNInitWait", TOKEN(emc_mrw_reset_ninit_wait) },
|
||||
{ "EmcAdrCfg1", TOKEN(emc_adr_cfg1) },
|
||||
{ "EmcAdrCfg", TOKEN(emc_adr_cfg) },
|
||||
{ "McEmemCfg", TOKEN(mc_emem_Cfg) },
|
||||
{ "McLowLatencyConfig", TOKEN(mc_lowlatency_config) },
|
||||
{ "EmcCfg2", TOKEN(emc_cfg2) },
|
||||
{ "EmcCfgDigDll", TOKEN(emc_cfg_dig_dll) },
|
||||
{ "EmcCfgClktrim0", TOKEN(emc_cfg_clktrim0) },
|
||||
{ "EmcCfgClktrim1", TOKEN(emc_cfg_clktrim1) },
|
||||
{ "EmcCfgClktrim2", TOKEN(emc_cfg_clktrim2) },
|
||||
{ "EmcCfg", TOKEN(emc_cfg) },
|
||||
{ "EmcDbg", TOKEN(emc_dbg) },
|
||||
{ "AhbArbitrationXbarCtrl", TOKEN(ahb_arbitration_xbar_ctrl) },
|
||||
{ "EmcDllXformDqs", TOKEN(emc_dll_xform_dqs) },
|
||||
{ "EmcDllXformQUse", TOKEN(emc_dll_xform_quse) },
|
||||
{ "WarmBootWait", TOKEN(warm_boot_wait) },
|
||||
{ "EmcCttTermCtrl", TOKEN(emc_ctt_term_ctrl) },
|
||||
{ "EmcOdtWrite", TOKEN(emc_odt_write) },
|
||||
{ "EmcOdtRead", TOKEN(emc_odt_read) },
|
||||
{ "EmcZcalRefCnt", TOKEN(emc_zcal_ref_cnt) },
|
||||
{ "EmcZcalWaitCnt", TOKEN(emc_zcal_wait_cnt) },
|
||||
{ "EmcZcalMrwCmd", TOKEN(emc_zcal_mrw_cmd) },
|
||||
{ "EmcMrwZqInitDev0", TOKEN(emc_mrw_zq_init_dev0) },
|
||||
{ "EmcMrwZqInitDev1", TOKEN(emc_mrw_zq_init_dev1) },
|
||||
{ "EmcMrwZqInitWait", TOKEN(emc_mrw_zq_init_wait) },
|
||||
{ "EmcDdr2Wait", TOKEN(emc_ddr2_wait) },
|
||||
{ "PmcDdrPwr", TOKEN(pmc_ddr_pwr) },
|
||||
{ "ApbMiscGpXm2CfgAPadCtrl", TOKEN(apb_misc_gp_xm2cfga_pad_ctrl) },
|
||||
{ "ApbMiscGpXm2CfgCPadCtrl2", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl2) },
|
||||
{ "ApbMiscGpXm2CfgCPadCtrl", TOKEN(apb_misc_gp_xm2cfgc_pad_ctrl) },
|
||||
{ "ApbMiscGpXm2CfgDPadCtrl2", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl2) },
|
||||
{ "ApbMiscGpXm2CfgDPadCtrl", TOKEN(apb_misc_gp_xm2cfgd_pad_ctrl) },
|
||||
{ "ApbMiscGpXm2ClkCfgPadCtrl", TOKEN(apb_misc_gp_xm2clkcfg_Pad_ctrl)},
|
||||
{ "ApbMiscGpXm2CompPadCtrl", TOKEN(apb_misc_gp_xm2comp_pad_ctrl) },
|
||||
{ "ApbMiscGpXm2VttGenPadCtrl", TOKEN(apb_misc_gp_xm2vttgen_pad_ctrl)},
|
||||
{ NULL, 0, 0, 0, NULL }
|
||||
};
|
||||
|
||||
static field_item s_nand_table[] =
|
||||
#undef TOKEN
|
||||
#define TOKEN(name) \
|
||||
token_##name, nvbct_lib_id_nand_##name, field_type_u32, NULL
|
||||
|
||||
field_item s_nand_table[] =
|
||||
{
|
||||
{ "ClockDivider", token_clock_divider, field_type_u32, NULL },
|
||||
{ "ClockDivider", TOKEN(clock_divider) },
|
||||
/* Note: NandTiming2 must appear before NandTiming, because NandTiming
|
||||
* is a prefix of NandTiming2 and would otherwise match first.
|
||||
*/
|
||||
{ "NandTiming2", token_nand_timing2, field_type_u32, NULL },
|
||||
{ "NandTiming", token_nand_timing, field_type_u32, NULL },
|
||||
{ "BlockSizeLog2", token_block_size_log2, field_type_u32, NULL },
|
||||
{ "PageSizeLog2", token_page_size_log2, field_type_u32, NULL },
|
||||
{ NULL, 0, 0, NULL }
|
||||
{ "NandTiming2", TOKEN(nand_timing2) },
|
||||
{ "NandTiming", TOKEN(nand_timing) },
|
||||
{ "BlockSizeLog2", TOKEN(block_size_log2) },
|
||||
{ "PageSizeLog2", TOKEN(page_size_log2) },
|
||||
{ NULL, 0, 0, 0, NULL }
|
||||
};
|
||||
|
||||
static field_item s_sdmmc_table[] =
|
||||
{
|
||||
{ "ClockDivider", token_clock_divider, field_type_u32, NULL },
|
||||
{ "DataWidth", token_data_width,
|
||||
field_type_enum, s_sdmmc_data_width_table },
|
||||
{ "MaxPowerClassSupported", token_max_power_class_supported,
|
||||
field_type_u32, NULL },
|
||||
#undef TOKEN
|
||||
#define TOKEN(name) \
|
||||
token_##name, nvbct_lib_id_sdmmc_##name, field_type_u32, NULL
|
||||
|
||||
{ NULL, 0, 0, NULL }
|
||||
field_item s_sdmmc_table[] =
|
||||
{
|
||||
{ "ClockDivider", TOKEN(clock_divider) },
|
||||
{ "DataWidth",
|
||||
token_data_width,
|
||||
nvbct_lib_id_sdmmc_data_width,
|
||||
field_type_enum,
|
||||
s_sdmmc_data_width_table },
|
||||
{ "MaxPowerClassSupported", TOKEN(max_power_class_supported) },
|
||||
{ NULL, 0, 0, 0, NULL }
|
||||
};
|
||||
|
||||
static field_item s_spiflash_table[] =
|
||||
{
|
||||
{ "ReadCommandTypeFast", token_read_command_type_fast,
|
||||
field_type_u8, NULL },
|
||||
{ "ClockDivider", token_clock_divider, field_type_u8, NULL },
|
||||
{ "ClockSource", token_clock_source,
|
||||
field_type_enum, s_spi_clock_source_table },
|
||||
#undef TOKEN
|
||||
#define TOKEN(name) \
|
||||
token_##name, nvbct_lib_id_spiflash_##name, field_type_u8, NULL
|
||||
|
||||
{ NULL, 0, 0, NULL }
|
||||
field_item s_spiflash_table[] =
|
||||
{
|
||||
{ "ReadCommandTypeFast", TOKEN(read_command_type_fast) },
|
||||
{ "ClockDivider", TOKEN(clock_divider) },
|
||||
{ "ClockSource",
|
||||
token_clock_source,
|
||||
nvbct_lib_id_spiflash_clock_source,
|
||||
field_type_enum,
|
||||
s_spi_clock_source_table },
|
||||
{ NULL, 0, 0, 0, NULL }
|
||||
};
|
||||
|
||||
static parse_subfield_item s_device_type_table[] =
|
||||
|
||||
14
parse.h
14
parse.h
@@ -202,6 +202,7 @@ typedef struct
|
||||
{
|
||||
char *name;
|
||||
u_int32_t token;
|
||||
u_int32_t enum_value;
|
||||
field_type type;
|
||||
enum_item *enum_table;
|
||||
} field_item;
|
||||
@@ -221,6 +222,19 @@ typedef struct
|
||||
process_function process;
|
||||
} parse_item;
|
||||
|
||||
/*
|
||||
* Provide access to enum and field tables. These tables are useful when
|
||||
* pretty printing a BCT file using bct_dump.
|
||||
*/
|
||||
extern enum_item s_devtype_table[];
|
||||
extern enum_item s_sdmmc_data_width_table[];
|
||||
extern enum_item s_spi_clock_source_table[];
|
||||
extern enum_item s_nvboot_memory_type_table[];
|
||||
extern field_item s_sdram_field_table[];
|
||||
extern field_item s_nand_table[];
|
||||
extern field_item s_sdmmc_table[];
|
||||
extern field_item s_spiflash_table[];
|
||||
|
||||
/*
|
||||
* Function prototypes
|
||||
*/
|
||||
|
||||
Reference in New Issue
Block a user