scottk/OpenCellular
1
0
Fork 0
mirror of https://github.com/Telecominfraproject/OpenCellular.git synced 2026-01-09 17:11:42 +00:00
Code Issues Packages Projects Releases Wiki Activity

chell: pmic: Delay disable of V0.85A

Browse Source 
Various voltage rails will be enabled / disabled by the PMIC when
GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
by approximately 25ms in order to allow V1.00A to sufficiently discharge
first.

BUG=chrome-os-partner:52047
TEST=Probe V1.00A and V0.85A during power-down, verify V1.00A discharges
faster than V0.85A.
BRANCH=glados

Change-Id: Ibbf4f989e1814e131dc373d2b5da9b6fa1ac9cce
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/337325
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2016-04-06 16:37:20 -07:00
committed by chrome-bot
parent 80680c7ffc
commit e6533d36a8
2 changed files with 38 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
board/chell/board.c
View File

@@ -475,3 +475,34 @@ static void board_handle_reboot(void)
; /* wait here */
}
DECLARE_HOOK(HOOK_INIT, board_handle_reboot, HOOK_PRIO_FIRST);
/*
* Various voltage rails will be enabled / disabled by the PMIC when
* GPIO_PMIC_SLP_SUS_L changes. We need to delay the disable of V0.85A
* by approximately 25ms in order to allow V1.00A to sufficiently discharge
* first.
*
* Therefore, after GPIO_PMIC_SLP_SUS_L goes high, ignore the state of
* the V12_EN pin: Keep V0.85A enabled.
*
* When GPIO_PMIC_SLP_SUS_L goes low, delay 25ms, and make V12_EN function
* as normal - this should result in V0.85A discharging immediately after the
* i2c write completes.
*/
void chipset_set_pmic_slp_sus_l(int level)
{
static int previous_level;
int val;
gpio_set_level(GPIO_PMIC_SLP_SUS_L, level);
if (previous_level != level) {
/* Rising edge: Force V0.85A enable. Falling: Pin control. */
val = level ? 0x80 : 0;
if (!level)
msleep(25);
i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x43, val);
previous_level = level;
}
}

9
power/skylake.c
View File

@@ -72,11 +72,16 @@ void chipset_force_shutdown(void)
}
}
__attribute__((weak)) void chipset_set_pmic_slp_sus_l(int level)
{
gpio_set_level(GPIO_PMIC_SLP_SUS_L, level);
}
static void chipset_force_g3(void)
{
CPRINTS("Forcing fake G3.");
gpio_set_level(GPIO_PMIC_SLP_SUS_L, 0);
chipset_set_pmic_slp_sus_l(0);
}
void chipset_reset(int cold_reset)
@@ -161,7 +166,7 @@ static void handle_slp_sus(enum power_state state)
return;
/* Always mimic PCH SLP_SUS request for all other states. */
gpio_set_level(GPIO_PMIC_SLP_SUS_L, gpio_get_level(GPIO_PCH_SLP_SUS_L));
chipset_set_pmic_slp_sus_l(gpio_get_level(GPIO_PCH_SLP_SUS_L));
}
#ifdef CONFIG_BOARD_HAS_RTC_RESET