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nuc: Add i2cscan and kbpress commands for FAFT.

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Add i2cscan and kbpress commands for FAFT.
Remove unnecessary i2c reading since there is no race condition.

Bugs fixed:
Fixed i2c_read_string bug since we shouldn't enable NACK if flag doesn't
contain I2C_XFER_STOP.
Fixed i2c_unwedge bug since the parameter should be port not controller.
Fixed state machine bug since we should restore bus state back to idle
if bus encountered timeout.

Modified drivers:
1. board.h: Add i2cscan and kbpress commands for FAFT.
2. i2c.c: Remove unnecessary reading since there is no race condition.
3. i2c.c: Fixed i2c_read_string and i2c_unwedge bugs.
4. i2c.c: Restore to idle state if bus encountered timeout.
5. board.h: Add CONFIG_LOW_POWER_IDLE for better power consumption.

BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
BRANCH=none

Change-Id: I98974f852cbbaec270c697feb8016b52550005bc
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/313393
Reviewed-by: Randall Spangler <rspangler@chromium.org>
This commit is contained in:
Mulin Chao
2015-11-20 16:13:16 +08:00
committed by chrome-bot
parent 70915b5012
commit e803e81114
2 changed files with 31 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
board/wheatley/board.h
View File

@@ -50,11 +50,12 @@
#define CONFIG_LID_ANGLE_SENSOR_BASE 0
#define CONFIG_LID_ANGLE_SENSOR_LID 2
#define CONFIG_LID_SWITCH
#define CONFIG_LOW_POWER_IDLE
#define CONFIG_POWER_BUTTON
#define CONFIG_POWER_BUTTON_X86
#define CONFIG_POWER_COMMON
/* All data won't fit in data RAM. So, moving boundary slightly. */
#define RAM_SHIFT_SIZE (4 * 1024)
#define RAM_SHIFT_SIZE (8 * 1024)
#undef CONFIG_RO_SIZE
#define CONFIG_RO_SIZE (96 * 1024 + RAM_SHIFT_SIZE)
#undef CONFIG_RAM_BASE
@@ -62,7 +63,7 @@
#undef CONFIG_RAM_SIZE
#define CONFIG_RAM_SIZE (0x00008000 - 0x800 - RAM_SHIFT_SIZE)
#define CONFIG_SCI_GPIO GPIO_PCH_SCI_L
/* We're space constrained on GLaDOS, so reduce the UART TX buffer size. */
/* We're space constrained on Wheatley, so reduce the UART TX buffer size. */
#undef CONFIG_UART_TX_BUF_SIZE
#define CONFIG_UART_TX_BUF_SIZE 512
#define CONFIG_USB_CHARGER
@@ -86,7 +87,7 @@
#define CONFIG_USBC_VCONN_SWAP
#define CONFIG_VBOOT_HASH
#define CONFIG_FLASH_SIZE 0x40000 /* 256 KB Flash used for EC */
#define CONFIG_FLASH_SIZE 0x80000 /* 512 KB Flash used for EC */
#define CONFIG_SPI_FLASH_W25X40
#define CONFIG_TEMP_SENSOR
@@ -139,12 +140,9 @@
/* Modules we want to exclude */
#undef CONFIG_PECI
#undef CONFIG_CMD_HASH
#undef CONFIG_CMD_I2C_SCAN
#undef CONFIG_CMD_KEYBOARD
#undef CONFIG_CMD_TEMP_SENSOR
#undef CONFIG_CMD_TIMERINFO
#undef CONFIG_CONSOLE_CMDHELP
#undef CONFIG_CONSOLE_HISTORY
#undef DEFERRABLE_MAX_COUNT
#define DEFERRABLE_MAX_COUNT 14

62
chip/npcx/i2c.c
View File

@@ -230,29 +230,21 @@ enum smb_error i2c_master_transaction(int controller)
}
} else if (p_status->oper_state == SMB_READ_SUSPEND) {
/* Need to read the other bytes from next transaction */
uint8_t data;
uint8_t timeout = 10; /* unit: us */
p_status->oper_state = SMB_READ_OPER;
/* wait for SDAST issue */
while (timeout > 0) {
if (IS_BIT_SET(NPCX_SMBST(controller),
NPCX_SMBST_SDAST))
break;
if (--timeout > 0)
usleep(10);
if (p_status->sz_rxbuf == 1) {
/*
* Since SCL is released after reading last byte from
* previous transaction, we have no chance to set NACK
* bit if the next transaction is only one byte. Master
* cannot generate STOP when the last byte is ACK during
* receiving.
*/
CPRINTS("I2C %d rxbuf size should exceed one byte in "
"2th transaction", controller);
p_status->err_code = SMB_BUS_ERROR;
i2c_recovery(controller);
return EC_ERROR_UNKNOWN;
}
if (timeout == 0)
return EC_ERROR_TIMEOUT;
/*
* Read first byte from SMBSDA in case SDAST interrupt occurs
* immediately before task_wait_event_mask() func
*/
I2C_READ_BYTE(controller, data);
CPRINTS("-R(%02x)", data);
/* Read to buffer */
p_status->rx_buf[p_status->idx_buf++] = data;
}
/* Generate a START condition */
@@ -274,6 +266,8 @@ enum smb_error i2c_master_transaction(int controller)
/* Recovery I2C controller */
i2c_recovery(controller);
p_status->err_code = SMB_TIMEOUT_ERROR;
/* Restore to idle status */
p_status->oper_state = SMB_IDLE;
}
/*
@@ -378,7 +372,8 @@ inline void i2c_handle_sda_irq(int controller)
* Receiving one byte only - set nack just
* before writing address byte
*/
if (p_status->sz_rxbuf == 1) {
if (p_status->sz_rxbuf == 1 &&
(p_status->flags & I2C_XFER_STOP)) {
I2C_NACK(controller);
CPUTS("-GNA");
}
@@ -405,6 +400,13 @@ inline void i2c_handle_sda_irq(int controller)
/* Stop should set before reading last byte */
I2C_STOP(controller);
CPUTS("-SP");
} else {
/*
* Disable interrupt before i2c master read SDA
* reg (stall SCL) and forbid SDAST generate
* interrupt until starting other transactions
*/
i2c_interrupt(controller, 0);
}
}
/* Check if byte-before-last is about to be read */
@@ -420,17 +422,6 @@ inline void i2c_handle_sda_irq(int controller)
}
}
/* Read last byte but flag don't include I2C_XFER_STOP */
if (p_status->idx_buf == p_status->sz_rxbuf-1) {
/*
* Disable interrupt before i2c master read SDA reg
* (stall SCL) and forbid SDAST generate interrupt
* until common layer start other transactions
*/
if (!(p_status->flags & I2C_XFER_STOP))
i2c_interrupt(controller, 0);
}
/* Read data for SMBSDA */
I2C_READ_BYTE(controller, data);
CPRINTS("-R(%02x)", data);
@@ -566,8 +557,8 @@ int chip_i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size,
if ((flags & I2C_XFER_START) && (i2c_bus_busy(ctrl)
|| (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
/* Attempt to unwedge the controller. */
i2c_unwedge(ctrl);
/* Attempt to unwedge the i2c port. */
i2c_unwedge(port);
/* recovery i2c controller */
i2c_recovery(ctrl);
/* Select port again for recovery */
@@ -770,3 +761,4 @@ static void i2c_init(void)
}
}
DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_INIT_I2C);