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cr50: enable highsec jittery clock

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The highsec jittery clock was breaking the USB peripheral, because it
would use bank values that mapped to frequencies less than 15MHz. This
change modifies stepx16 to keep the bankvalues mapped to frequencies
above 18MHz to ensure the USB peripheral can work with the high
security jittery clock.

BUG=chrome-os-partner:53952
BRANCH=none
TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin

Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/356192
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
This commit is contained in:
Mary Ruthven
2016-06-24 14:24:23 -07:00
committed by chrome-bot
parent 9a644c429a
commit e84a71fe67
2 changed files with 2 additions and 3 deletions
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3
board/cr50/board.c
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@@ -130,8 +130,7 @@ static void board_init(void)
init_timers();
init_interrupts();
init_trng();
/* TODO(crosbug.com/p/53952): enable jittery clock */
/* init_jittery_clock(1); */
init_jittery_clock(1);
init_runlevel(PERMISSION_MEDIUM);
/* Initialize NvMem partitions */
nvmem_init();

2
chip/g/jitter.c
View File

@@ -27,7 +27,7 @@ void init_jittery_clock(int highsec)
int bank;
if (highsec)
stepx16 = 0xff - trimfast;
stepx16 = (delta * 7) >> 1;
else
stepx16 = 2 * (trim48 - trimfast);