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clock: Fix clock_wait_cycles() asm

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The 'cycles' register will be clobbered by our macro, so it must be
specified as an output operand that may also be used as input.

BUG=chrome-os-partner:60000
BRANCH=gru,strago,glados
TEST=Build + burn wheatley, verify alignment exception is not
encountered on boot. Also verify produced assembly is still correct:

100a89a6:       2303            movs    r3, #3
100a89a8:       3b01            subs    r3, #1
100a89aa:       d1fd            bne.n   100a89a8

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I1be03a006967aed6970dbac5d98a19a31e0b7d49
Reviewed-on: https://chromium-review.googlesource.com/412441
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Shawn Nematbakhsh
2016-11-17 12:56:13 -08:00
committed by chrome-bot
parent 7c6d8d40f1
commit e97073a20d
3 changed files with 6 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
chip/lm4/clock.c
View File

@@ -140,8 +140,8 @@ void clock_enable_pll(int enable, int notify)
void clock_wait_cycles(uint32_t cycles)
{
asm("1: subs %0, #1\n"
" bne 1b\n" :: "r"(cycles));
asm volatile("1: subs %0, #1\n"
" bne 1b\n" : "+r"(cycles));
}
int clock_get_freq(void)

4
chip/mec1322/clock.c
View File

@@ -49,8 +49,8 @@ static int freq = 48000000;
void clock_wait_cycles(uint32_t cycles)
{
asm("1: subs %0, #1\n"
" bne 1b\n" :: "r"(cycles));
asm volatile("1: subs %0, #1\n"
" bne 1b\n" : "+r"(cycles));
}
int clock_get_freq(void)

4
chip/npcx/clock.c
View File

@@ -227,8 +227,8 @@ int clock_get_apb2_freq(void)
*/
void clock_wait_cycles(uint32_t cycles)
{
asm("1: subs %0, #1\n"
" bne 1b\n" : : "r"(cycles));
asm volatile("1: subs %0, #1\n"
" bne 1b\n" : "+r"(cycles));
}
#ifdef CONFIG_LOW_POWER_IDLE